/* * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). * * Redistribution and use in source and binary forms, with or without modification, are * permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software must display * the following acknowledgement: "This product includes software developed by * Microchip Technology Inc. and its subsidiaries." * 4. Microchip's name may not be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _PIC16F1455_INC_ #define _PIC16F1455_INC_ /* * Assembly Header file for the Microchip PIC Microcontroller * PIC16F1455 */ /* * Device Registers */ // Register: INDF0 INDF0 equ 0000h // bitfield definitions INDF0_INDF0_POSN equ 0000h INDF0_INDF0_POSITION equ 0000h INDF0_INDF0_SIZE equ 0008h INDF0_INDF0_LENGTH equ 0008h INDF0_INDF0_MASK equ 00FFh // Register: INDF1 INDF1 equ 0001h // bitfield definitions INDF1_INDF1_POSN equ 0000h INDF1_INDF1_POSITION equ 0000h INDF1_INDF1_SIZE equ 0008h INDF1_INDF1_LENGTH equ 0008h INDF1_INDF1_MASK equ 00FFh // Register: PCL PCL equ 0002h // bitfield definitions PCL_PCL_POSN equ 0000h PCL_PCL_POSITION equ 0000h PCL_PCL_SIZE equ 0008h PCL_PCL_LENGTH equ 0008h PCL_PCL_MASK equ 00FFh // Register: STATUS STATUS equ 0003h // bitfield definitions STATUS_C_POSN equ 0000h STATUS_C_POSITION equ 0000h STATUS_C_SIZE equ 0001h STATUS_C_LENGTH equ 0001h STATUS_C_MASK equ 0001h STATUS_DC_POSN equ 0001h STATUS_DC_POSITION equ 0001h STATUS_DC_SIZE equ 0001h STATUS_DC_LENGTH equ 0001h STATUS_DC_MASK equ 0002h STATUS_Z_POSN equ 0002h STATUS_Z_POSITION equ 0002h STATUS_Z_SIZE equ 0001h STATUS_Z_LENGTH equ 0001h STATUS_Z_MASK equ 0004h STATUS_nPD_POSN equ 0003h STATUS_nPD_POSITION equ 0003h STATUS_nPD_SIZE equ 0001h STATUS_nPD_LENGTH equ 0001h STATUS_nPD_MASK equ 0008h STATUS_nTO_POSN equ 0004h STATUS_nTO_POSITION equ 0004h STATUS_nTO_SIZE equ 0001h STATUS_nTO_LENGTH equ 0001h STATUS_nTO_MASK equ 0010h STATUS_CARRY_POSN equ 0000h STATUS_CARRY_POSITION equ 0000h STATUS_CARRY_SIZE equ 0001h STATUS_CARRY_LENGTH equ 0001h STATUS_CARRY_MASK equ 0001h STATUS_ZERO_POSN equ 0002h STATUS_ZERO_POSITION equ 0002h STATUS_ZERO_SIZE equ 0001h STATUS_ZERO_LENGTH equ 0001h STATUS_ZERO_MASK equ 0004h // Register: FSR0L FSR0L equ 0004h // bitfield definitions FSR0L_FSR0L_POSN equ 0000h FSR0L_FSR0L_POSITION equ 0000h FSR0L_FSR0L_SIZE equ 0008h FSR0L_FSR0L_LENGTH equ 0008h FSR0L_FSR0L_MASK equ 00FFh // Register: FSR0H FSR0H equ 0005h // bitfield definitions FSR0H_FSR0H_POSN equ 0000h FSR0H_FSR0H_POSITION equ 0000h FSR0H_FSR0H_SIZE equ 0008h FSR0H_FSR0H_LENGTH equ 0008h FSR0H_FSR0H_MASK equ 00FFh // Register: FSR1L FSR1L equ 0006h // bitfield definitions FSR1L_FSR1L_POSN equ 0000h FSR1L_FSR1L_POSITION equ 0000h FSR1L_FSR1L_SIZE equ 0008h FSR1L_FSR1L_LENGTH equ 0008h FSR1L_FSR1L_MASK equ 00FFh // Register: FSR1H FSR1H equ 0007h // bitfield definitions FSR1H_FSR1H_POSN equ 0000h FSR1H_FSR1H_POSITION equ 0000h FSR1H_FSR1H_SIZE equ 0008h FSR1H_FSR1H_LENGTH equ 0008h FSR1H_FSR1H_MASK equ 00FFh // Register: BSR BSR equ 0008h // bitfield definitions BSR_BSR_POSN equ 0000h BSR_BSR_POSITION equ 0000h BSR_BSR_SIZE equ 0005h BSR_BSR_LENGTH equ 0005h BSR_BSR_MASK equ 001Fh BSR_BSR0_POSN equ 0000h BSR_BSR0_POSITION equ 0000h BSR_BSR0_SIZE equ 0001h BSR_BSR0_LENGTH equ 0001h BSR_BSR0_MASK equ 0001h BSR_BSR1_POSN equ 0001h BSR_BSR1_POSITION equ 0001h BSR_BSR1_SIZE equ 0001h BSR_BSR1_LENGTH equ 0001h BSR_BSR1_MASK equ 0002h BSR_BSR2_POSN equ 0002h BSR_BSR2_POSITION equ 0002h BSR_BSR2_SIZE equ 0001h BSR_BSR2_LENGTH equ 0001h BSR_BSR2_MASK equ 0004h BSR_BSR3_POSN equ 0003h BSR_BSR3_POSITION equ 0003h BSR_BSR3_SIZE equ 0001h BSR_BSR3_LENGTH equ 0001h BSR_BSR3_MASK equ 0008h BSR_BSR4_POSN equ 0004h BSR_BSR4_POSITION equ 0004h BSR_BSR4_SIZE equ 0001h BSR_BSR4_LENGTH equ 0001h BSR_BSR4_MASK equ 0010h // Register: WREG WREG equ 0009h // bitfield definitions WREG_WREG0_POSN equ 0000h WREG_WREG0_POSITION equ 0000h WREG_WREG0_SIZE equ 0008h WREG_WREG0_LENGTH equ 0008h WREG_WREG0_MASK equ 00FFh // Register: PCLATH PCLATH equ 000Ah // bitfield definitions PCLATH_PCLATH_POSN equ 0000h PCLATH_PCLATH_POSITION equ 0000h PCLATH_PCLATH_SIZE equ 0007h PCLATH_PCLATH_LENGTH equ 0007h PCLATH_PCLATH_MASK equ 007Fh // Register: INTCON INTCON equ 000Bh // bitfield definitions INTCON_IOCIF_POSN equ 0000h INTCON_IOCIF_POSITION equ 0000h INTCON_IOCIF_SIZE equ 0001h INTCON_IOCIF_LENGTH equ 0001h INTCON_IOCIF_MASK equ 0001h INTCON_INTF_POSN equ 0001h INTCON_INTF_POSITION equ 0001h INTCON_INTF_SIZE equ 0001h INTCON_INTF_LENGTH equ 0001h INTCON_INTF_MASK equ 0002h INTCON_TMR0IF_POSN equ 0002h INTCON_TMR0IF_POSITION equ 0002h INTCON_TMR0IF_SIZE equ 0001h INTCON_TMR0IF_LENGTH equ 0001h INTCON_TMR0IF_MASK equ 0004h INTCON_IOCIE_POSN equ 0003h INTCON_IOCIE_POSITION equ 0003h INTCON_IOCIE_SIZE equ 0001h INTCON_IOCIE_LENGTH equ 0001h INTCON_IOCIE_MASK equ 0008h INTCON_INTE_POSN equ 0004h INTCON_INTE_POSITION equ 0004h INTCON_INTE_SIZE equ 0001h INTCON_INTE_LENGTH equ 0001h INTCON_INTE_MASK equ 0010h INTCON_TMR0IE_POSN equ 0005h INTCON_TMR0IE_POSITION equ 0005h INTCON_TMR0IE_SIZE equ 0001h INTCON_TMR0IE_LENGTH equ 0001h INTCON_TMR0IE_MASK equ 0020h INTCON_PEIE_POSN equ 0006h INTCON_PEIE_POSITION equ 0006h INTCON_PEIE_SIZE equ 0001h INTCON_PEIE_LENGTH equ 0001h INTCON_PEIE_MASK equ 0040h INTCON_GIE_POSN equ 0007h INTCON_GIE_POSITION equ 0007h INTCON_GIE_SIZE equ 0001h INTCON_GIE_LENGTH equ 0001h INTCON_GIE_MASK equ 0080h INTCON_T0IF_POSN equ 0002h INTCON_T0IF_POSITION equ 0002h INTCON_T0IF_SIZE equ 0001h INTCON_T0IF_LENGTH equ 0001h INTCON_T0IF_MASK equ 0004h INTCON_T0IE_POSN equ 0005h INTCON_T0IE_POSITION equ 0005h INTCON_T0IE_SIZE equ 0001h INTCON_T0IE_LENGTH equ 0001h INTCON_T0IE_MASK equ 0020h // Register: PORTA PORTA equ 000Ch // bitfield definitions PORTA_RA0_POSN equ 0000h PORTA_RA0_POSITION equ 0000h PORTA_RA0_SIZE equ 0001h PORTA_RA0_LENGTH equ 0001h PORTA_RA0_MASK equ 0001h PORTA_RA1_POSN equ 0001h PORTA_RA1_POSITION equ 0001h PORTA_RA1_SIZE equ 0001h PORTA_RA1_LENGTH equ 0001h PORTA_RA1_MASK equ 0002h PORTA_RA3_POSN equ 0003h PORTA_RA3_POSITION equ 0003h PORTA_RA3_SIZE equ 0001h PORTA_RA3_LENGTH equ 0001h PORTA_RA3_MASK equ 0008h PORTA_RA4_POSN equ 0004h PORTA_RA4_POSITION equ 0004h PORTA_RA4_SIZE equ 0001h PORTA_RA4_LENGTH equ 0001h PORTA_RA4_MASK equ 0010h PORTA_RA5_POSN equ 0005h PORTA_RA5_POSITION equ 0005h PORTA_RA5_SIZE equ 0001h PORTA_RA5_LENGTH equ 0001h PORTA_RA5_MASK equ 0020h // Register: PORTC PORTC equ 000Eh // bitfield definitions PORTC_RC0_POSN equ 0000h PORTC_RC0_POSITION equ 0000h PORTC_RC0_SIZE equ 0001h PORTC_RC0_LENGTH equ 0001h PORTC_RC0_MASK equ 0001h PORTC_RC1_POSN equ 0001h PORTC_RC1_POSITION equ 0001h PORTC_RC1_SIZE equ 0001h PORTC_RC1_LENGTH equ 0001h PORTC_RC1_MASK equ 0002h PORTC_RC2_POSN equ 0002h PORTC_RC2_POSITION equ 0002h PORTC_RC2_SIZE equ 0001h PORTC_RC2_LENGTH equ 0001h PORTC_RC2_MASK equ 0004h PORTC_RC3_POSN equ 0003h PORTC_RC3_POSITION equ 0003h PORTC_RC3_SIZE equ 0001h PORTC_RC3_LENGTH equ 0001h PORTC_RC3_MASK equ 0008h PORTC_RC4_POSN equ 0004h PORTC_RC4_POSITION equ 0004h PORTC_RC4_SIZE equ 0001h PORTC_RC4_LENGTH equ 0001h PORTC_RC4_MASK equ 0010h PORTC_RC5_POSN equ 0005h PORTC_RC5_POSITION equ 0005h PORTC_RC5_SIZE equ 0001h PORTC_RC5_LENGTH equ 0001h PORTC_RC5_MASK equ 0020h // Register: PIR1 PIR1 equ 0011h // bitfield definitions PIR1_TMR1IF_POSN equ 0000h PIR1_TMR1IF_POSITION equ 0000h PIR1_TMR1IF_SIZE equ 0001h PIR1_TMR1IF_LENGTH equ 0001h PIR1_TMR1IF_MASK equ 0001h PIR1_TMR2IF_POSN equ 0001h PIR1_TMR2IF_POSITION equ 0001h PIR1_TMR2IF_SIZE equ 0001h PIR1_TMR2IF_LENGTH equ 0001h PIR1_TMR2IF_MASK equ 0002h PIR1_SSP1IF_POSN equ 0003h PIR1_SSP1IF_POSITION equ 0003h PIR1_SSP1IF_SIZE equ 0001h PIR1_SSP1IF_LENGTH equ 0001h PIR1_SSP1IF_MASK equ 0008h PIR1_TXIF_POSN equ 0004h PIR1_TXIF_POSITION equ 0004h PIR1_TXIF_SIZE equ 0001h PIR1_TXIF_LENGTH equ 0001h PIR1_TXIF_MASK equ 0010h PIR1_RCIF_POSN equ 0005h PIR1_RCIF_POSITION equ 0005h PIR1_RCIF_SIZE equ 0001h PIR1_RCIF_LENGTH equ 0001h PIR1_RCIF_MASK equ 0020h PIR1_ADIF_POSN equ 0006h PIR1_ADIF_POSITION equ 0006h PIR1_ADIF_SIZE equ 0001h PIR1_ADIF_LENGTH equ 0001h PIR1_ADIF_MASK equ 0040h PIR1_TMR1GIF_POSN equ 0007h PIR1_TMR1GIF_POSITION equ 0007h PIR1_TMR1GIF_SIZE equ 0001h PIR1_TMR1GIF_LENGTH equ 0001h PIR1_TMR1GIF_MASK equ 0080h // Register: PIR2 PIR2 equ 0012h // bitfield definitions PIR2_ACTIF_POSN equ 0001h PIR2_ACTIF_POSITION equ 0001h PIR2_ACTIF_SIZE equ 0001h PIR2_ACTIF_LENGTH equ 0001h PIR2_ACTIF_MASK equ 0002h PIR2_USBIF_POSN equ 0002h PIR2_USBIF_POSITION equ 0002h PIR2_USBIF_SIZE equ 0001h PIR2_USBIF_LENGTH equ 0001h PIR2_USBIF_MASK equ 0004h PIR2_BCL1IF_POSN equ 0003h PIR2_BCL1IF_POSITION equ 0003h PIR2_BCL1IF_SIZE equ 0001h PIR2_BCL1IF_LENGTH equ 0001h PIR2_BCL1IF_MASK equ 0008h PIR2_C1IF_POSN equ 0005h PIR2_C1IF_POSITION equ 0005h PIR2_C1IF_SIZE equ 0001h PIR2_C1IF_LENGTH equ 0001h PIR2_C1IF_MASK equ 0020h PIR2_C2IF_POSN equ 0006h PIR2_C2IF_POSITION equ 0006h PIR2_C2IF_SIZE equ 0001h PIR2_C2IF_LENGTH equ 0001h PIR2_C2IF_MASK equ 0040h PIR2_OSFIF_POSN equ 0007h PIR2_OSFIF_POSITION equ 0007h PIR2_OSFIF_SIZE equ 0001h PIR2_OSFIF_LENGTH equ 0001h PIR2_OSFIF_MASK equ 0080h // Register: TMR0 TMR0 equ 0015h // bitfield definitions TMR0_TMR0_POSN equ 0000h TMR0_TMR0_POSITION equ 0000h TMR0_TMR0_SIZE equ 0008h TMR0_TMR0_LENGTH equ 0008h TMR0_TMR0_MASK equ 00FFh // Register: TMR1L TMR1L equ 0016h // bitfield definitions TMR1L_TMR1L_POSN equ 0000h TMR1L_TMR1L_POSITION equ 0000h TMR1L_TMR1L_SIZE equ 0008h TMR1L_TMR1L_LENGTH equ 0008h TMR1L_TMR1L_MASK equ 00FFh // Register: TMR1H TMR1H equ 0017h // bitfield definitions TMR1H_TMR1H_POSN equ 0000h TMR1H_TMR1H_POSITION equ 0000h TMR1H_TMR1H_SIZE equ 0008h TMR1H_TMR1H_LENGTH equ 0008h TMR1H_TMR1H_MASK equ 00FFh // Register: T1CON T1CON equ 0018h // bitfield definitions T1CON_TMR1ON_POSN equ 0000h T1CON_TMR1ON_POSITION equ 0000h T1CON_TMR1ON_SIZE equ 0001h T1CON_TMR1ON_LENGTH equ 0001h T1CON_TMR1ON_MASK equ 0001h T1CON_nT1SYNC_POSN equ 0002h T1CON_nT1SYNC_POSITION equ 0002h T1CON_nT1SYNC_SIZE equ 0001h T1CON_nT1SYNC_LENGTH equ 0001h T1CON_nT1SYNC_MASK equ 0004h T1CON_T1OSCEN_POSN equ 0003h T1CON_T1OSCEN_POSITION equ 0003h T1CON_T1OSCEN_SIZE equ 0001h T1CON_T1OSCEN_LENGTH equ 0001h T1CON_T1OSCEN_MASK equ 0008h T1CON_T1CKPS_POSN equ 0004h T1CON_T1CKPS_POSITION equ 0004h T1CON_T1CKPS_SIZE equ 0002h T1CON_T1CKPS_LENGTH equ 0002h T1CON_T1CKPS_MASK equ 0030h T1CON_TMR1CS_POSN equ 0006h T1CON_TMR1CS_POSITION equ 0006h T1CON_TMR1CS_SIZE equ 0002h T1CON_TMR1CS_LENGTH equ 0002h T1CON_TMR1CS_MASK equ 00C0h T1CON_T1CKPS0_POSN equ 0004h T1CON_T1CKPS0_POSITION equ 0004h T1CON_T1CKPS0_SIZE equ 0001h T1CON_T1CKPS0_LENGTH equ 0001h T1CON_T1CKPS0_MASK equ 0010h T1CON_T1CKPS1_POSN equ 0005h T1CON_T1CKPS1_POSITION equ 0005h T1CON_T1CKPS1_SIZE equ 0001h T1CON_T1CKPS1_LENGTH equ 0001h T1CON_T1CKPS1_MASK equ 0020h T1CON_TMR1CS0_POSN equ 0006h T1CON_TMR1CS0_POSITION equ 0006h T1CON_TMR1CS0_SIZE equ 0001h T1CON_TMR1CS0_LENGTH equ 0001h T1CON_TMR1CS0_MASK equ 0040h T1CON_TMR1CS1_POSN equ 0007h T1CON_TMR1CS1_POSITION equ 0007h T1CON_TMR1CS1_SIZE equ 0001h T1CON_TMR1CS1_LENGTH equ 0001h T1CON_TMR1CS1_MASK equ 0080h // Register: T1GCON T1GCON equ 0019h // bitfield definitions T1GCON_T1GSS_POSN equ 0000h T1GCON_T1GSS_POSITION equ 0000h T1GCON_T1GSS_SIZE equ 0002h T1GCON_T1GSS_LENGTH equ 0002h T1GCON_T1GSS_MASK equ 0003h T1GCON_T1GVAL_POSN equ 0002h T1GCON_T1GVAL_POSITION equ 0002h T1GCON_T1GVAL_SIZE equ 0001h T1GCON_T1GVAL_LENGTH equ 0001h T1GCON_T1GVAL_MASK equ 0004h T1GCON_T1GGO_nDONE_POSN equ 0003h T1GCON_T1GGO_nDONE_POSITION equ 0003h T1GCON_T1GGO_nDONE_SIZE equ 0001h T1GCON_T1GGO_nDONE_LENGTH equ 0001h T1GCON_T1GGO_nDONE_MASK equ 0008h T1GCON_T1GSPM_POSN equ 0004h T1GCON_T1GSPM_POSITION equ 0004h T1GCON_T1GSPM_SIZE equ 0001h T1GCON_T1GSPM_LENGTH equ 0001h T1GCON_T1GSPM_MASK equ 0010h T1GCON_T1GTM_POSN equ 0005h T1GCON_T1GTM_POSITION equ 0005h T1GCON_T1GTM_SIZE equ 0001h T1GCON_T1GTM_LENGTH equ 0001h T1GCON_T1GTM_MASK equ 0020h T1GCON_T1GPOL_POSN equ 0006h T1GCON_T1GPOL_POSITION equ 0006h T1GCON_T1GPOL_SIZE equ 0001h T1GCON_T1GPOL_LENGTH equ 0001h T1GCON_T1GPOL_MASK equ 0040h T1GCON_TMR1GE_POSN equ 0007h T1GCON_TMR1GE_POSITION equ 0007h T1GCON_TMR1GE_SIZE equ 0001h T1GCON_TMR1GE_LENGTH equ 0001h T1GCON_TMR1GE_MASK equ 0080h T1GCON_T1GSS0_POSN equ 0000h T1GCON_T1GSS0_POSITION equ 0000h T1GCON_T1GSS0_SIZE equ 0001h T1GCON_T1GSS0_LENGTH equ 0001h T1GCON_T1GSS0_MASK equ 0001h T1GCON_T1GSS1_POSN equ 0001h T1GCON_T1GSS1_POSITION equ 0001h T1GCON_T1GSS1_SIZE equ 0001h T1GCON_T1GSS1_LENGTH equ 0001h T1GCON_T1GSS1_MASK equ 0002h // Register: TMR2 TMR2 equ 001Ah // bitfield definitions TMR2_TMR2_POSN equ 0000h TMR2_TMR2_POSITION equ 0000h TMR2_TMR2_SIZE equ 0008h TMR2_TMR2_LENGTH equ 0008h TMR2_TMR2_MASK equ 00FFh // Register: PR2 PR2 equ 001Bh // bitfield definitions PR2_PR2_POSN equ 0000h PR2_PR2_POSITION equ 0000h PR2_PR2_SIZE equ 0008h PR2_PR2_LENGTH equ 0008h PR2_PR2_MASK equ 00FFh // Register: T2CON T2CON equ 001Ch // bitfield definitions T2CON_T2CKPS_POSN equ 0000h T2CON_T2CKPS_POSITION equ 0000h T2CON_T2CKPS_SIZE equ 0002h T2CON_T2CKPS_LENGTH equ 0002h T2CON_T2CKPS_MASK equ 0003h T2CON_TMR2ON_POSN equ 0002h T2CON_TMR2ON_POSITION equ 0002h T2CON_TMR2ON_SIZE equ 0001h T2CON_TMR2ON_LENGTH equ 0001h T2CON_TMR2ON_MASK equ 0004h T2CON_T2OUTPS_POSN equ 0003h T2CON_T2OUTPS_POSITION equ 0003h T2CON_T2OUTPS_SIZE equ 0004h T2CON_T2OUTPS_LENGTH equ 0004h T2CON_T2OUTPS_MASK equ 0078h T2CON_T2CKPS0_POSN equ 0000h T2CON_T2CKPS0_POSITION equ 0000h T2CON_T2CKPS0_SIZE equ 0001h T2CON_T2CKPS0_LENGTH equ 0001h T2CON_T2CKPS0_MASK equ 0001h T2CON_T2CKPS1_POSN equ 0001h T2CON_T2CKPS1_POSITION equ 0001h T2CON_T2CKPS1_SIZE equ 0001h T2CON_T2CKPS1_LENGTH equ 0001h T2CON_T2CKPS1_MASK equ 0002h T2CON_T2OUTPS0_POSN equ 0003h T2CON_T2OUTPS0_POSITION equ 0003h T2CON_T2OUTPS0_SIZE equ 0001h T2CON_T2OUTPS0_LENGTH equ 0001h T2CON_T2OUTPS0_MASK equ 0008h T2CON_T2OUTPS1_POSN equ 0004h T2CON_T2OUTPS1_POSITION equ 0004h T2CON_T2OUTPS1_SIZE equ 0001h T2CON_T2OUTPS1_LENGTH equ 0001h T2CON_T2OUTPS1_MASK equ 0010h T2CON_T2OUTPS2_POSN equ 0005h T2CON_T2OUTPS2_POSITION equ 0005h T2CON_T2OUTPS2_SIZE equ 0001h T2CON_T2OUTPS2_LENGTH equ 0001h T2CON_T2OUTPS2_MASK equ 0020h T2CON_T2OUTPS3_POSN equ 0006h T2CON_T2OUTPS3_POSITION equ 0006h T2CON_T2OUTPS3_SIZE equ 0001h T2CON_T2OUTPS3_LENGTH equ 0001h T2CON_T2OUTPS3_MASK equ 0040h // Register: TRISA TRISA equ 008Ch // bitfield definitions TRISA_TRISA4_POSN equ 0004h TRISA_TRISA4_POSITION equ 0004h TRISA_TRISA4_SIZE equ 0001h TRISA_TRISA4_LENGTH equ 0001h TRISA_TRISA4_MASK equ 0010h TRISA_TRISA5_POSN equ 0005h TRISA_TRISA5_POSITION equ 0005h TRISA_TRISA5_SIZE equ 0001h TRISA_TRISA5_LENGTH equ 0001h TRISA_TRISA5_MASK equ 0020h // Register: TRISC TRISC equ 008Eh // bitfield definitions TRISC_TRISC0_POSN equ 0000h TRISC_TRISC0_POSITION equ 0000h TRISC_TRISC0_SIZE equ 0001h TRISC_TRISC0_LENGTH equ 0001h TRISC_TRISC0_MASK equ 0001h TRISC_TRISC1_POSN equ 0001h TRISC_TRISC1_POSITION equ 0001h TRISC_TRISC1_SIZE equ 0001h TRISC_TRISC1_LENGTH equ 0001h TRISC_TRISC1_MASK equ 0002h TRISC_TRISC2_POSN equ 0002h TRISC_TRISC2_POSITION equ 0002h TRISC_TRISC2_SIZE equ 0001h TRISC_TRISC2_LENGTH equ 0001h TRISC_TRISC2_MASK equ 0004h TRISC_TRISC3_POSN equ 0003h TRISC_TRISC3_POSITION equ 0003h TRISC_TRISC3_SIZE equ 0001h TRISC_TRISC3_LENGTH equ 0001h TRISC_TRISC3_MASK equ 0008h TRISC_TRISC4_POSN equ 0004h TRISC_TRISC4_POSITION equ 0004h TRISC_TRISC4_SIZE equ 0001h TRISC_TRISC4_LENGTH equ 0001h TRISC_TRISC4_MASK equ 0010h TRISC_TRISC5_POSN equ 0005h TRISC_TRISC5_POSITION equ 0005h TRISC_TRISC5_SIZE equ 0001h TRISC_TRISC5_LENGTH equ 0001h TRISC_TRISC5_MASK equ 0020h // Register: PIE1 PIE1 equ 0091h // bitfield definitions PIE1_TMR1IE_POSN equ 0000h PIE1_TMR1IE_POSITION equ 0000h PIE1_TMR1IE_SIZE equ 0001h PIE1_TMR1IE_LENGTH equ 0001h PIE1_TMR1IE_MASK equ 0001h PIE1_TMR2IE_POSN equ 0001h PIE1_TMR2IE_POSITION equ 0001h PIE1_TMR2IE_SIZE equ 0001h PIE1_TMR2IE_LENGTH equ 0001h PIE1_TMR2IE_MASK equ 0002h PIE1_SSP1IE_POSN equ 0003h PIE1_SSP1IE_POSITION equ 0003h PIE1_SSP1IE_SIZE equ 0001h PIE1_SSP1IE_LENGTH equ 0001h PIE1_SSP1IE_MASK equ 0008h PIE1_TXIE_POSN equ 0004h PIE1_TXIE_POSITION equ 0004h PIE1_TXIE_SIZE equ 0001h PIE1_TXIE_LENGTH equ 0001h PIE1_TXIE_MASK equ 0010h PIE1_RCIE_POSN equ 0005h PIE1_RCIE_POSITION equ 0005h PIE1_RCIE_SIZE equ 0001h PIE1_RCIE_LENGTH equ 0001h PIE1_RCIE_MASK equ 0020h PIE1_ADIE_POSN equ 0006h PIE1_ADIE_POSITION equ 0006h PIE1_ADIE_SIZE equ 0001h PIE1_ADIE_LENGTH equ 0001h PIE1_ADIE_MASK equ 0040h PIE1_TMR1GIE_POSN equ 0007h PIE1_TMR1GIE_POSITION equ 0007h PIE1_TMR1GIE_SIZE equ 0001h PIE1_TMR1GIE_LENGTH equ 0001h PIE1_TMR1GIE_MASK equ 0080h // Register: PIE2 PIE2 equ 0092h // bitfield definitions PIE2_ACTIE_POSN equ 0001h PIE2_ACTIE_POSITION equ 0001h PIE2_ACTIE_SIZE equ 0001h PIE2_ACTIE_LENGTH equ 0001h PIE2_ACTIE_MASK equ 0002h PIE2_USBIE_POSN equ 0002h PIE2_USBIE_POSITION equ 0002h PIE2_USBIE_SIZE equ 0001h PIE2_USBIE_LENGTH equ 0001h PIE2_USBIE_MASK equ 0004h PIE2_BCL1IE_POSN equ 0003h PIE2_BCL1IE_POSITION equ 0003h PIE2_BCL1IE_SIZE equ 0001h PIE2_BCL1IE_LENGTH equ 0001h PIE2_BCL1IE_MASK equ 0008h PIE2_C1IE_POSN equ 0005h PIE2_C1IE_POSITION equ 0005h PIE2_C1IE_SIZE equ 0001h PIE2_C1IE_LENGTH equ 0001h PIE2_C1IE_MASK equ 0020h PIE2_C2IE_POSN equ 0006h PIE2_C2IE_POSITION equ 0006h PIE2_C2IE_SIZE equ 0001h PIE2_C2IE_LENGTH equ 0001h PIE2_C2IE_MASK equ 0040h PIE2_OSFIE_POSN equ 0007h PIE2_OSFIE_POSITION equ 0007h PIE2_OSFIE_SIZE equ 0001h PIE2_OSFIE_LENGTH equ 0001h PIE2_OSFIE_MASK equ 0080h // Register: OPTION_REG OPTION_REG equ 0095h // bitfield definitions OPTION_REG_PS_POSN equ 0000h OPTION_REG_PS_POSITION equ 0000h OPTION_REG_PS_SIZE equ 0003h OPTION_REG_PS_LENGTH equ 0003h OPTION_REG_PS_MASK equ 0007h OPTION_REG_PSA_POSN equ 0003h OPTION_REG_PSA_POSITION equ 0003h OPTION_REG_PSA_SIZE equ 0001h OPTION_REG_PSA_LENGTH equ 0001h OPTION_REG_PSA_MASK equ 0008h OPTION_REG_TMR0SE_POSN equ 0004h OPTION_REG_TMR0SE_POSITION equ 0004h OPTION_REG_TMR0SE_SIZE equ 0001h OPTION_REG_TMR0SE_LENGTH equ 0001h OPTION_REG_TMR0SE_MASK equ 0010h OPTION_REG_TMR0CS_POSN equ 0005h OPTION_REG_TMR0CS_POSITION equ 0005h OPTION_REG_TMR0CS_SIZE equ 0001h OPTION_REG_TMR0CS_LENGTH equ 0001h OPTION_REG_TMR0CS_MASK equ 0020h OPTION_REG_INTEDG_POSN equ 0006h OPTION_REG_INTEDG_POSITION equ 0006h OPTION_REG_INTEDG_SIZE equ 0001h OPTION_REG_INTEDG_LENGTH equ 0001h OPTION_REG_INTEDG_MASK equ 0040h OPTION_REG_nWPUEN_POSN equ 0007h OPTION_REG_nWPUEN_POSITION equ 0007h OPTION_REG_nWPUEN_SIZE equ 0001h OPTION_REG_nWPUEN_LENGTH equ 0001h OPTION_REG_nWPUEN_MASK equ 0080h OPTION_REG_PS0_POSN equ 0000h OPTION_REG_PS0_POSITION equ 0000h OPTION_REG_PS0_SIZE equ 0001h OPTION_REG_PS0_LENGTH equ 0001h OPTION_REG_PS0_MASK equ 0001h OPTION_REG_PS1_POSN equ 0001h OPTION_REG_PS1_POSITION equ 0001h OPTION_REG_PS1_SIZE equ 0001h OPTION_REG_PS1_LENGTH equ 0001h OPTION_REG_PS1_MASK equ 0002h OPTION_REG_PS2_POSN equ 0002h OPTION_REG_PS2_POSITION equ 0002h OPTION_REG_PS2_SIZE equ 0001h OPTION_REG_PS2_LENGTH equ 0001h OPTION_REG_PS2_MASK equ 0004h OPTION_REG_T0SE_POSN equ 0004h OPTION_REG_T0SE_POSITION equ 0004h OPTION_REG_T0SE_SIZE equ 0001h OPTION_REG_T0SE_LENGTH equ 0001h OPTION_REG_T0SE_MASK equ 0010h OPTION_REG_T0CS_POSN equ 0005h OPTION_REG_T0CS_POSITION equ 0005h OPTION_REG_T0CS_SIZE equ 0001h OPTION_REG_T0CS_LENGTH equ 0001h OPTION_REG_T0CS_MASK equ 0020h // Register: PCON PCON equ 0096h // bitfield definitions PCON_nBOR_POSN equ 0000h PCON_nBOR_POSITION equ 0000h PCON_nBOR_SIZE equ 0001h PCON_nBOR_LENGTH equ 0001h PCON_nBOR_MASK equ 0001h PCON_nPOR_POSN equ 0001h PCON_nPOR_POSITION equ 0001h PCON_nPOR_SIZE equ 0001h PCON_nPOR_LENGTH equ 0001h PCON_nPOR_MASK equ 0002h PCON_nRI_POSN equ 0002h PCON_nRI_POSITION equ 0002h PCON_nRI_SIZE equ 0001h PCON_nRI_LENGTH equ 0001h PCON_nRI_MASK equ 0004h PCON_nRMCLR_POSN equ 0003h PCON_nRMCLR_POSITION equ 0003h PCON_nRMCLR_SIZE equ 0001h PCON_nRMCLR_LENGTH equ 0001h PCON_nRMCLR_MASK equ 0008h PCON_nRWDT_POSN equ 0004h PCON_nRWDT_POSITION equ 0004h PCON_nRWDT_SIZE equ 0001h PCON_nRWDT_LENGTH equ 0001h PCON_nRWDT_MASK equ 0010h PCON_STKUNF_POSN equ 0006h PCON_STKUNF_POSITION equ 0006h PCON_STKUNF_SIZE equ 0001h PCON_STKUNF_LENGTH equ 0001h PCON_STKUNF_MASK equ 0040h PCON_STKOVF_POSN equ 0007h PCON_STKOVF_POSITION equ 0007h PCON_STKOVF_SIZE equ 0001h PCON_STKOVF_LENGTH equ 0001h PCON_STKOVF_MASK equ 0080h // Register: WDTCON WDTCON equ 0097h // bitfield definitions WDTCON_SWDTEN_POSN equ 0000h WDTCON_SWDTEN_POSITION equ 0000h WDTCON_SWDTEN_SIZE equ 0001h WDTCON_SWDTEN_LENGTH equ 0001h WDTCON_SWDTEN_MASK equ 0001h WDTCON_WDTPS_POSN equ 0001h WDTCON_WDTPS_POSITION equ 0001h WDTCON_WDTPS_SIZE equ 0005h WDTCON_WDTPS_LENGTH equ 0005h WDTCON_WDTPS_MASK equ 003Eh WDTCON_WDTPS0_POSN equ 0001h WDTCON_WDTPS0_POSITION equ 0001h WDTCON_WDTPS0_SIZE equ 0001h WDTCON_WDTPS0_LENGTH equ 0001h WDTCON_WDTPS0_MASK equ 0002h WDTCON_WDTPS1_POSN equ 0002h WDTCON_WDTPS1_POSITION equ 0002h WDTCON_WDTPS1_SIZE equ 0001h WDTCON_WDTPS1_LENGTH equ 0001h WDTCON_WDTPS1_MASK equ 0004h WDTCON_WDTPS2_POSN equ 0003h WDTCON_WDTPS2_POSITION equ 0003h WDTCON_WDTPS2_SIZE equ 0001h WDTCON_WDTPS2_LENGTH equ 0001h WDTCON_WDTPS2_MASK equ 0008h WDTCON_WDTPS3_POSN equ 0004h WDTCON_WDTPS3_POSITION equ 0004h WDTCON_WDTPS3_SIZE equ 0001h WDTCON_WDTPS3_LENGTH equ 0001h WDTCON_WDTPS3_MASK equ 0010h WDTCON_WDTPS4_POSN equ 0005h WDTCON_WDTPS4_POSITION equ 0005h WDTCON_WDTPS4_SIZE equ 0001h WDTCON_WDTPS4_LENGTH equ 0001h WDTCON_WDTPS4_MASK equ 0020h // Register: OSCTUNE OSCTUNE equ 0098h // bitfield definitions OSCTUNE_TUN_POSN equ 0000h OSCTUNE_TUN_POSITION equ 0000h OSCTUNE_TUN_SIZE equ 0007h OSCTUNE_TUN_LENGTH equ 0007h OSCTUNE_TUN_MASK equ 007Fh OSCTUNE_TUN0_POSN equ 0000h OSCTUNE_TUN0_POSITION equ 0000h OSCTUNE_TUN0_SIZE equ 0001h OSCTUNE_TUN0_LENGTH equ 0001h OSCTUNE_TUN0_MASK equ 0001h OSCTUNE_TUN1_POSN equ 0001h OSCTUNE_TUN1_POSITION equ 0001h OSCTUNE_TUN1_SIZE equ 0001h OSCTUNE_TUN1_LENGTH equ 0001h OSCTUNE_TUN1_MASK equ 0002h OSCTUNE_TUN2_POSN equ 0002h OSCTUNE_TUN2_POSITION equ 0002h OSCTUNE_TUN2_SIZE equ 0001h OSCTUNE_TUN2_LENGTH equ 0001h OSCTUNE_TUN2_MASK equ 0004h OSCTUNE_TUN3_POSN equ 0003h OSCTUNE_TUN3_POSITION equ 0003h OSCTUNE_TUN3_SIZE equ 0001h OSCTUNE_TUN3_LENGTH equ 0001h OSCTUNE_TUN3_MASK equ 0008h OSCTUNE_TUN4_POSN equ 0004h OSCTUNE_TUN4_POSITION equ 0004h OSCTUNE_TUN4_SIZE equ 0001h OSCTUNE_TUN4_LENGTH equ 0001h OSCTUNE_TUN4_MASK equ 0010h OSCTUNE_TUN5_POSN equ 0005h OSCTUNE_TUN5_POSITION equ 0005h OSCTUNE_TUN5_SIZE equ 0001h OSCTUNE_TUN5_LENGTH equ 0001h OSCTUNE_TUN5_MASK equ 0020h OSCTUNE_TUN6_POSN equ 0006h OSCTUNE_TUN6_POSITION equ 0006h OSCTUNE_TUN6_SIZE equ 0001h OSCTUNE_TUN6_LENGTH equ 0001h OSCTUNE_TUN6_MASK equ 0040h // Register: OSCCON OSCCON equ 0099h // bitfield definitions OSCCON_SCS_POSN equ 0000h OSCCON_SCS_POSITION equ 0000h OSCCON_SCS_SIZE equ 0002h OSCCON_SCS_LENGTH equ 0002h OSCCON_SCS_MASK equ 0003h OSCCON_IRCF_POSN equ 0002h OSCCON_IRCF_POSITION equ 0002h OSCCON_IRCF_SIZE equ 0004h OSCCON_IRCF_LENGTH equ 0004h OSCCON_IRCF_MASK equ 003Ch OSCCON_SPLLMULT_POSN equ 0006h OSCCON_SPLLMULT_POSITION equ 0006h OSCCON_SPLLMULT_SIZE equ 0001h OSCCON_SPLLMULT_LENGTH equ 0001h OSCCON_SPLLMULT_MASK equ 0040h OSCCON_SPLLEN_POSN equ 0007h OSCCON_SPLLEN_POSITION equ 0007h OSCCON_SPLLEN_SIZE equ 0001h OSCCON_SPLLEN_LENGTH equ 0001h OSCCON_SPLLEN_MASK equ 0080h OSCCON_SCS0_POSN equ 0000h OSCCON_SCS0_POSITION equ 0000h OSCCON_SCS0_SIZE equ 0001h OSCCON_SCS0_LENGTH equ 0001h OSCCON_SCS0_MASK equ 0001h OSCCON_SCS1_POSN equ 0001h OSCCON_SCS1_POSITION equ 0001h OSCCON_SCS1_SIZE equ 0001h OSCCON_SCS1_LENGTH equ 0001h OSCCON_SCS1_MASK equ 0002h OSCCON_IRCF0_POSN equ 0002h OSCCON_IRCF0_POSITION equ 0002h OSCCON_IRCF0_SIZE equ 0001h OSCCON_IRCF0_LENGTH equ 0001h OSCCON_IRCF0_MASK equ 0004h OSCCON_IRCF1_POSN equ 0003h OSCCON_IRCF1_POSITION equ 0003h OSCCON_IRCF1_SIZE equ 0001h OSCCON_IRCF1_LENGTH equ 0001h OSCCON_IRCF1_MASK equ 0008h OSCCON_IRCF2_POSN equ 0004h OSCCON_IRCF2_POSITION equ 0004h OSCCON_IRCF2_SIZE equ 0001h OSCCON_IRCF2_LENGTH equ 0001h OSCCON_IRCF2_MASK equ 0010h OSCCON_IRCF3_POSN equ 0005h OSCCON_IRCF3_POSITION equ 0005h OSCCON_IRCF3_SIZE equ 0001h OSCCON_IRCF3_LENGTH equ 0001h OSCCON_IRCF3_MASK equ 0020h // Register: OSCSTAT OSCSTAT equ 009Ah // bitfield definitions OSCSTAT_HFIOFS_POSN equ 0000h OSCSTAT_HFIOFS_POSITION equ 0000h OSCSTAT_HFIOFS_SIZE equ 0001h OSCSTAT_HFIOFS_LENGTH equ 0001h OSCSTAT_HFIOFS_MASK equ 0001h OSCSTAT_LFIOFR_POSN equ 0001h OSCSTAT_LFIOFR_POSITION equ 0001h OSCSTAT_LFIOFR_SIZE equ 0001h OSCSTAT_LFIOFR_LENGTH equ 0001h OSCSTAT_LFIOFR_MASK equ 0002h OSCSTAT_HFIOFR_POSN equ 0004h OSCSTAT_HFIOFR_POSITION equ 0004h OSCSTAT_HFIOFR_SIZE equ 0001h OSCSTAT_HFIOFR_LENGTH equ 0001h OSCSTAT_HFIOFR_MASK equ 0010h OSCSTAT_OSTS_POSN equ 0005h OSCSTAT_OSTS_POSITION equ 0005h OSCSTAT_OSTS_SIZE equ 0001h OSCSTAT_OSTS_LENGTH equ 0001h OSCSTAT_OSTS_MASK equ 0020h OSCSTAT_PLLRDY_POSN equ 0006h OSCSTAT_PLLRDY_POSITION equ 0006h OSCSTAT_PLLRDY_SIZE equ 0001h OSCSTAT_PLLRDY_LENGTH equ 0001h OSCSTAT_PLLRDY_MASK equ 0040h OSCSTAT_SOSCR_POSN equ 0007h OSCSTAT_SOSCR_POSITION equ 0007h OSCSTAT_SOSCR_SIZE equ 0001h OSCSTAT_SOSCR_LENGTH equ 0001h OSCSTAT_SOSCR_MASK equ 0080h // Register: ADRESL ADRESL equ 009Bh // bitfield definitions ADRESL_ADRESL_POSN equ 0000h ADRESL_ADRESL_POSITION equ 0000h ADRESL_ADRESL_SIZE equ 0008h ADRESL_ADRESL_LENGTH equ 0008h ADRESL_ADRESL_MASK equ 00FFh // Register: ADRESH ADRESH equ 009Ch // bitfield definitions ADRESH_ADRESH_POSN equ 0000h ADRESH_ADRESH_POSITION equ 0000h ADRESH_ADRESH_SIZE equ 0008h ADRESH_ADRESH_LENGTH equ 0008h ADRESH_ADRESH_MASK equ 00FFh // Register: ADCON0 ADCON0 equ 009Dh // bitfield definitions ADCON0_ADON_POSN equ 0000h ADCON0_ADON_POSITION equ 0000h ADCON0_ADON_SIZE equ 0001h ADCON0_ADON_LENGTH equ 0001h ADCON0_ADON_MASK equ 0001h ADCON0_GO_nDONE_POSN equ 0001h ADCON0_GO_nDONE_POSITION equ 0001h ADCON0_GO_nDONE_SIZE equ 0001h ADCON0_GO_nDONE_LENGTH equ 0001h ADCON0_GO_nDONE_MASK equ 0002h ADCON0_CHS_POSN equ 0002h ADCON0_CHS_POSITION equ 0002h ADCON0_CHS_SIZE equ 0005h ADCON0_CHS_LENGTH equ 0005h ADCON0_CHS_MASK equ 007Ch ADCON0_ADGO_POSN equ 0001h ADCON0_ADGO_POSITION equ 0001h ADCON0_ADGO_SIZE equ 0001h ADCON0_ADGO_LENGTH equ 0001h ADCON0_ADGO_MASK equ 0002h ADCON0_CHS0_POSN equ 0002h ADCON0_CHS0_POSITION equ 0002h ADCON0_CHS0_SIZE equ 0001h ADCON0_CHS0_LENGTH equ 0001h ADCON0_CHS0_MASK equ 0004h ADCON0_CHS1_POSN equ 0003h ADCON0_CHS1_POSITION equ 0003h ADCON0_CHS1_SIZE equ 0001h ADCON0_CHS1_LENGTH equ 0001h ADCON0_CHS1_MASK equ 0008h ADCON0_CHS2_POSN equ 0004h ADCON0_CHS2_POSITION equ 0004h ADCON0_CHS2_SIZE equ 0001h ADCON0_CHS2_LENGTH equ 0001h ADCON0_CHS2_MASK equ 0010h ADCON0_CHS3_POSN equ 0005h ADCON0_CHS3_POSITION equ 0005h ADCON0_CHS3_SIZE equ 0001h ADCON0_CHS3_LENGTH equ 0001h ADCON0_CHS3_MASK equ 0020h ADCON0_CHS4_POSN equ 0006h ADCON0_CHS4_POSITION equ 0006h ADCON0_CHS4_SIZE equ 0001h ADCON0_CHS4_LENGTH equ 0001h ADCON0_CHS4_MASK equ 0040h ADCON0_GO_POSN equ 0001h ADCON0_GO_POSITION equ 0001h ADCON0_GO_SIZE equ 0001h ADCON0_GO_LENGTH equ 0001h ADCON0_GO_MASK equ 0002h // Register: ADCON1 ADCON1 equ 009Eh // bitfield definitions ADCON1_ADPREF_POSN equ 0000h ADCON1_ADPREF_POSITION equ 0000h ADCON1_ADPREF_SIZE equ 0002h ADCON1_ADPREF_LENGTH equ 0002h ADCON1_ADPREF_MASK equ 0003h ADCON1_ADCS_POSN equ 0004h ADCON1_ADCS_POSITION equ 0004h ADCON1_ADCS_SIZE equ 0003h ADCON1_ADCS_LENGTH equ 0003h ADCON1_ADCS_MASK equ 0070h ADCON1_ADFM_POSN equ 0007h ADCON1_ADFM_POSITION equ 0007h ADCON1_ADFM_SIZE equ 0001h ADCON1_ADFM_LENGTH equ 0001h ADCON1_ADFM_MASK equ 0080h ADCON1_ADPREF0_POSN equ 0000h ADCON1_ADPREF0_POSITION equ 0000h ADCON1_ADPREF0_SIZE equ 0001h ADCON1_ADPREF0_LENGTH equ 0001h ADCON1_ADPREF0_MASK equ 0001h ADCON1_ADPREF1_POSN equ 0001h ADCON1_ADPREF1_POSITION equ 0001h ADCON1_ADPREF1_SIZE equ 0001h ADCON1_ADPREF1_LENGTH equ 0001h ADCON1_ADPREF1_MASK equ 0002h ADCON1_ADCS0_POSN equ 0004h ADCON1_ADCS0_POSITION equ 0004h ADCON1_ADCS0_SIZE equ 0001h ADCON1_ADCS0_LENGTH equ 0001h ADCON1_ADCS0_MASK equ 0010h ADCON1_ADCS1_POSN equ 0005h ADCON1_ADCS1_POSITION equ 0005h ADCON1_ADCS1_SIZE equ 0001h ADCON1_ADCS1_LENGTH equ 0001h ADCON1_ADCS1_MASK equ 0020h ADCON1_ADCS2_POSN equ 0006h ADCON1_ADCS2_POSITION equ 0006h ADCON1_ADCS2_SIZE equ 0001h ADCON1_ADCS2_LENGTH equ 0001h ADCON1_ADCS2_MASK equ 0040h // Register: ADCON2 ADCON2 equ 009Fh // bitfield definitions ADCON2_TRIGSEL_POSN equ 0004h ADCON2_TRIGSEL_POSITION equ 0004h ADCON2_TRIGSEL_SIZE equ 0003h ADCON2_TRIGSEL_LENGTH equ 0003h ADCON2_TRIGSEL_MASK equ 0070h ADCON2_TRIGSEL0_POSN equ 0004h ADCON2_TRIGSEL0_POSITION equ 0004h ADCON2_TRIGSEL0_SIZE equ 0001h ADCON2_TRIGSEL0_LENGTH equ 0001h ADCON2_TRIGSEL0_MASK equ 0010h ADCON2_TRIGSEL1_POSN equ 0005h ADCON2_TRIGSEL1_POSITION equ 0005h ADCON2_TRIGSEL1_SIZE equ 0001h ADCON2_TRIGSEL1_LENGTH equ 0001h ADCON2_TRIGSEL1_MASK equ 0020h ADCON2_TRIGSEL2_POSN equ 0006h ADCON2_TRIGSEL2_POSITION equ 0006h ADCON2_TRIGSEL2_SIZE equ 0001h ADCON2_TRIGSEL2_LENGTH equ 0001h ADCON2_TRIGSEL2_MASK equ 0040h // Register: LATA LATA equ 010Ch // bitfield definitions LATA_LATA4_POSN equ 0004h LATA_LATA4_POSITION equ 0004h LATA_LATA4_SIZE equ 0001h LATA_LATA4_LENGTH equ 0001h LATA_LATA4_MASK equ 0010h LATA_LATA5_POSN equ 0005h LATA_LATA5_POSITION equ 0005h LATA_LATA5_SIZE equ 0001h LATA_LATA5_LENGTH equ 0001h LATA_LATA5_MASK equ 0020h // Register: LATC LATC equ 010Eh // bitfield definitions LATC_LATC0_POSN equ 0000h LATC_LATC0_POSITION equ 0000h LATC_LATC0_SIZE equ 0001h LATC_LATC0_LENGTH equ 0001h LATC_LATC0_MASK equ 0001h LATC_LATC1_POSN equ 0001h LATC_LATC1_POSITION equ 0001h LATC_LATC1_SIZE equ 0001h LATC_LATC1_LENGTH equ 0001h LATC_LATC1_MASK equ 0002h LATC_LATC2_POSN equ 0002h LATC_LATC2_POSITION equ 0002h LATC_LATC2_SIZE equ 0001h LATC_LATC2_LENGTH equ 0001h LATC_LATC2_MASK equ 0004h LATC_LATC3_POSN equ 0003h LATC_LATC3_POSITION equ 0003h LATC_LATC3_SIZE equ 0001h LATC_LATC3_LENGTH equ 0001h LATC_LATC3_MASK equ 0008h LATC_LATC4_POSN equ 0004h LATC_LATC4_POSITION equ 0004h LATC_LATC4_SIZE equ 0001h LATC_LATC4_LENGTH equ 0001h LATC_LATC4_MASK equ 0010h LATC_LATC5_POSN equ 0005h LATC_LATC5_POSITION equ 0005h LATC_LATC5_SIZE equ 0001h LATC_LATC5_LENGTH equ 0001h LATC_LATC5_MASK equ 0020h // Register: CM1CON0 CM1CON0 equ 0111h // bitfield definitions CM1CON0_C1SYNC_POSN equ 0000h CM1CON0_C1SYNC_POSITION equ 0000h CM1CON0_C1SYNC_SIZE equ 0001h CM1CON0_C1SYNC_LENGTH equ 0001h CM1CON0_C1SYNC_MASK equ 0001h CM1CON0_C1HYS_POSN equ 0001h CM1CON0_C1HYS_POSITION equ 0001h CM1CON0_C1HYS_SIZE equ 0001h CM1CON0_C1HYS_LENGTH equ 0001h CM1CON0_C1HYS_MASK equ 0002h CM1CON0_C1SP_POSN equ 0002h CM1CON0_C1SP_POSITION equ 0002h CM1CON0_C1SP_SIZE equ 0001h CM1CON0_C1SP_LENGTH equ 0001h CM1CON0_C1SP_MASK equ 0004h CM1CON0_C1POL_POSN equ 0004h CM1CON0_C1POL_POSITION equ 0004h CM1CON0_C1POL_SIZE equ 0001h CM1CON0_C1POL_LENGTH equ 0001h CM1CON0_C1POL_MASK equ 0010h CM1CON0_C1OE_POSN equ 0005h CM1CON0_C1OE_POSITION equ 0005h CM1CON0_C1OE_SIZE equ 0001h CM1CON0_C1OE_LENGTH equ 0001h CM1CON0_C1OE_MASK equ 0020h CM1CON0_C1OUT_POSN equ 0006h CM1CON0_C1OUT_POSITION equ 0006h CM1CON0_C1OUT_SIZE equ 0001h CM1CON0_C1OUT_LENGTH equ 0001h CM1CON0_C1OUT_MASK equ 0040h CM1CON0_C1ON_POSN equ 0007h CM1CON0_C1ON_POSITION equ 0007h CM1CON0_C1ON_SIZE equ 0001h CM1CON0_C1ON_LENGTH equ 0001h CM1CON0_C1ON_MASK equ 0080h // Register: CM1CON1 CM1CON1 equ 0112h // bitfield definitions CM1CON1_C1NCH0_POSN equ 0000h CM1CON1_C1NCH0_POSITION equ 0000h CM1CON1_C1NCH0_SIZE equ 0001h CM1CON1_C1NCH0_LENGTH equ 0001h CM1CON1_C1NCH0_MASK equ 0001h CM1CON1_C1NCH1_POSN equ 0001h CM1CON1_C1NCH1_POSITION equ 0001h CM1CON1_C1NCH1_SIZE equ 0001h CM1CON1_C1NCH1_LENGTH equ 0001h CM1CON1_C1NCH1_MASK equ 0002h CM1CON1_C1NCH2_POSN equ 0002h CM1CON1_C1NCH2_POSITION equ 0002h CM1CON1_C1NCH2_SIZE equ 0001h CM1CON1_C1NCH2_LENGTH equ 0001h CM1CON1_C1NCH2_MASK equ 0004h CM1CON1_C1PCH0_POSN equ 0004h CM1CON1_C1PCH0_POSITION equ 0004h CM1CON1_C1PCH0_SIZE equ 0001h CM1CON1_C1PCH0_LENGTH equ 0001h CM1CON1_C1PCH0_MASK equ 0010h CM1CON1_C1PCH1_POSN equ 0005h CM1CON1_C1PCH1_POSITION equ 0005h CM1CON1_C1PCH1_SIZE equ 0001h CM1CON1_C1PCH1_LENGTH equ 0001h CM1CON1_C1PCH1_MASK equ 0020h CM1CON1_C1INTN_POSN equ 0006h CM1CON1_C1INTN_POSITION equ 0006h CM1CON1_C1INTN_SIZE equ 0001h CM1CON1_C1INTN_LENGTH equ 0001h CM1CON1_C1INTN_MASK equ 0040h CM1CON1_C1INTP_POSN equ 0007h CM1CON1_C1INTP_POSITION equ 0007h CM1CON1_C1INTP_SIZE equ 0001h CM1CON1_C1INTP_LENGTH equ 0001h CM1CON1_C1INTP_MASK equ 0080h CM1CON1_C1NCH_POSN equ 0000h CM1CON1_C1NCH_POSITION equ 0000h CM1CON1_C1NCH_SIZE equ 0003h CM1CON1_C1NCH_LENGTH equ 0003h CM1CON1_C1NCH_MASK equ 0007h CM1CON1_C1PCH_POSN equ 0004h CM1CON1_C1PCH_POSITION equ 0004h CM1CON1_C1PCH_SIZE equ 0002h CM1CON1_C1PCH_LENGTH equ 0002h CM1CON1_C1PCH_MASK equ 0030h // Register: CM2CON0 CM2CON0 equ 0113h // bitfield definitions CM2CON0_C2SYNC_POSN equ 0000h CM2CON0_C2SYNC_POSITION equ 0000h CM2CON0_C2SYNC_SIZE equ 0001h CM2CON0_C2SYNC_LENGTH equ 0001h CM2CON0_C2SYNC_MASK equ 0001h CM2CON0_C2HYS_POSN equ 0001h CM2CON0_C2HYS_POSITION equ 0001h CM2CON0_C2HYS_SIZE equ 0001h CM2CON0_C2HYS_LENGTH equ 0001h CM2CON0_C2HYS_MASK equ 0002h CM2CON0_C2SP_POSN equ 0002h CM2CON0_C2SP_POSITION equ 0002h CM2CON0_C2SP_SIZE equ 0001h CM2CON0_C2SP_LENGTH equ 0001h CM2CON0_C2SP_MASK equ 0004h CM2CON0_C2POL_POSN equ 0004h CM2CON0_C2POL_POSITION equ 0004h CM2CON0_C2POL_SIZE equ 0001h CM2CON0_C2POL_LENGTH equ 0001h CM2CON0_C2POL_MASK equ 0010h CM2CON0_C2OE_POSN equ 0005h CM2CON0_C2OE_POSITION equ 0005h CM2CON0_C2OE_SIZE equ 0001h CM2CON0_C2OE_LENGTH equ 0001h CM2CON0_C2OE_MASK equ 0020h CM2CON0_C2OUT_POSN equ 0006h CM2CON0_C2OUT_POSITION equ 0006h CM2CON0_C2OUT_SIZE equ 0001h CM2CON0_C2OUT_LENGTH equ 0001h CM2CON0_C2OUT_MASK equ 0040h CM2CON0_C2ON_POSN equ 0007h CM2CON0_C2ON_POSITION equ 0007h CM2CON0_C2ON_SIZE equ 0001h CM2CON0_C2ON_LENGTH equ 0001h CM2CON0_C2ON_MASK equ 0080h // Register: CM2CON1 CM2CON1 equ 0114h // bitfield definitions CM2CON1_C2NCH0_POSN equ 0000h CM2CON1_C2NCH0_POSITION equ 0000h CM2CON1_C2NCH0_SIZE equ 0001h CM2CON1_C2NCH0_LENGTH equ 0001h CM2CON1_C2NCH0_MASK equ 0001h CM2CON1_C2NCH1_POSN equ 0001h CM2CON1_C2NCH1_POSITION equ 0001h CM2CON1_C2NCH1_SIZE equ 0001h CM2CON1_C2NCH1_LENGTH equ 0001h CM2CON1_C2NCH1_MASK equ 0002h CM2CON1_C2NCH2_POSN equ 0002h CM2CON1_C2NCH2_POSITION equ 0002h CM2CON1_C2NCH2_SIZE equ 0001h CM2CON1_C2NCH2_LENGTH equ 0001h CM2CON1_C2NCH2_MASK equ 0004h CM2CON1_C2PCH0_POSN equ 0004h CM2CON1_C2PCH0_POSITION equ 0004h CM2CON1_C2PCH0_SIZE equ 0001h CM2CON1_C2PCH0_LENGTH equ 0001h CM2CON1_C2PCH0_MASK equ 0010h CM2CON1_C2PCH1_POSN equ 0005h CM2CON1_C2PCH1_POSITION equ 0005h CM2CON1_C2PCH1_SIZE equ 0001h CM2CON1_C2PCH1_LENGTH equ 0001h CM2CON1_C2PCH1_MASK equ 0020h CM2CON1_C2INTN_POSN equ 0006h CM2CON1_C2INTN_POSITION equ 0006h CM2CON1_C2INTN_SIZE equ 0001h CM2CON1_C2INTN_LENGTH equ 0001h CM2CON1_C2INTN_MASK equ 0040h CM2CON1_C2INTP_POSN equ 0007h CM2CON1_C2INTP_POSITION equ 0007h CM2CON1_C2INTP_SIZE equ 0001h CM2CON1_C2INTP_LENGTH equ 0001h CM2CON1_C2INTP_MASK equ 0080h CM2CON1_C2NCH_POSN equ 0000h CM2CON1_C2NCH_POSITION equ 0000h CM2CON1_C2NCH_SIZE equ 0003h CM2CON1_C2NCH_LENGTH equ 0003h CM2CON1_C2NCH_MASK equ 0007h CM2CON1_C2PCH_POSN equ 0004h CM2CON1_C2PCH_POSITION equ 0004h CM2CON1_C2PCH_SIZE equ 0002h CM2CON1_C2PCH_LENGTH equ 0002h CM2CON1_C2PCH_MASK equ 0030h // Register: CMOUT CMOUT equ 0115h // bitfield definitions CMOUT_MC1OUT_POSN equ 0000h CMOUT_MC1OUT_POSITION equ 0000h CMOUT_MC1OUT_SIZE equ 0001h CMOUT_MC1OUT_LENGTH equ 0001h CMOUT_MC1OUT_MASK equ 0001h CMOUT_MC2OUT_POSN equ 0001h CMOUT_MC2OUT_POSITION equ 0001h CMOUT_MC2OUT_SIZE equ 0001h CMOUT_MC2OUT_LENGTH equ 0001h CMOUT_MC2OUT_MASK equ 0002h // Register: BORCON BORCON equ 0116h // bitfield definitions BORCON_BORRDY_POSN equ 0000h BORCON_BORRDY_POSITION equ 0000h BORCON_BORRDY_SIZE equ 0001h BORCON_BORRDY_LENGTH equ 0001h BORCON_BORRDY_MASK equ 0001h BORCON_BORFS_POSN equ 0006h BORCON_BORFS_POSITION equ 0006h BORCON_BORFS_SIZE equ 0001h BORCON_BORFS_LENGTH equ 0001h BORCON_BORFS_MASK equ 0040h BORCON_SBOREN_POSN equ 0007h BORCON_SBOREN_POSITION equ 0007h BORCON_SBOREN_SIZE equ 0001h BORCON_SBOREN_LENGTH equ 0001h BORCON_SBOREN_MASK equ 0080h // Register: FVRCON FVRCON equ 0117h // bitfield definitions FVRCON_ADFVR_POSN equ 0000h FVRCON_ADFVR_POSITION equ 0000h FVRCON_ADFVR_SIZE equ 0002h FVRCON_ADFVR_LENGTH equ 0002h FVRCON_ADFVR_MASK equ 0003h FVRCON_CDAFVR_POSN equ 0002h FVRCON_CDAFVR_POSITION equ 0002h FVRCON_CDAFVR_SIZE equ 0002h FVRCON_CDAFVR_LENGTH equ 0002h FVRCON_CDAFVR_MASK equ 000Ch FVRCON_FVRRDY_POSN equ 0006h FVRCON_FVRRDY_POSITION equ 0006h FVRCON_FVRRDY_SIZE equ 0001h FVRCON_FVRRDY_LENGTH equ 0001h FVRCON_FVRRDY_MASK equ 0040h FVRCON_FVREN_POSN equ 0007h FVRCON_FVREN_POSITION equ 0007h FVRCON_FVREN_SIZE equ 0001h FVRCON_FVREN_LENGTH equ 0001h FVRCON_FVREN_MASK equ 0080h FVRCON_ADFVR0_POSN equ 0000h FVRCON_ADFVR0_POSITION equ 0000h FVRCON_ADFVR0_SIZE equ 0001h FVRCON_ADFVR0_LENGTH equ 0001h FVRCON_ADFVR0_MASK equ 0001h FVRCON_ADFVR1_POSN equ 0001h FVRCON_ADFVR1_POSITION equ 0001h FVRCON_ADFVR1_SIZE equ 0001h FVRCON_ADFVR1_LENGTH equ 0001h FVRCON_ADFVR1_MASK equ 0002h FVRCON_CDAFVR0_POSN equ 0002h FVRCON_CDAFVR0_POSITION equ 0002h FVRCON_CDAFVR0_SIZE equ 0001h FVRCON_CDAFVR0_LENGTH equ 0001h FVRCON_CDAFVR0_MASK equ 0004h FVRCON_CDAFVR1_POSN equ 0003h FVRCON_CDAFVR1_POSITION equ 0003h FVRCON_CDAFVR1_SIZE equ 0001h FVRCON_CDAFVR1_LENGTH equ 0001h FVRCON_CDAFVR1_MASK equ 0008h // Register: DACCON0 DACCON0 equ 0118h // bitfield definitions DACCON0_D1PSS_POSN equ 0002h DACCON0_D1PSS_POSITION equ 0002h DACCON0_D1PSS_SIZE equ 0002h DACCON0_D1PSS_LENGTH equ 0002h DACCON0_D1PSS_MASK equ 000Ch DACCON0_DACOE2_POSN equ 0004h DACCON0_DACOE2_POSITION equ 0004h DACCON0_DACOE2_SIZE equ 0001h DACCON0_DACOE2_LENGTH equ 0001h DACCON0_DACOE2_MASK equ 0010h DACCON0_DACOE1_POSN equ 0005h DACCON0_DACOE1_POSITION equ 0005h DACCON0_DACOE1_SIZE equ 0001h DACCON0_DACOE1_LENGTH equ 0001h DACCON0_DACOE1_MASK equ 0020h DACCON0_DACEN_POSN equ 0007h DACCON0_DACEN_POSITION equ 0007h DACCON0_DACEN_SIZE equ 0001h DACCON0_DACEN_LENGTH equ 0001h DACCON0_DACEN_MASK equ 0080h DACCON0_D1PSS0_POSN equ 0002h DACCON0_D1PSS0_POSITION equ 0002h DACCON0_D1PSS0_SIZE equ 0001h DACCON0_D1PSS0_LENGTH equ 0001h DACCON0_D1PSS0_MASK equ 0004h DACCON0_D1PSS1_POSN equ 0003h DACCON0_D1PSS1_POSITION equ 0003h DACCON0_D1PSS1_SIZE equ 0001h DACCON0_D1PSS1_LENGTH equ 0001h DACCON0_D1PSS1_MASK equ 0008h // Register: DACCON1 DACCON1 equ 0119h // bitfield definitions DACCON1_DACR_POSN equ 0000h DACCON1_DACR_POSITION equ 0000h DACCON1_DACR_SIZE equ 0005h DACCON1_DACR_LENGTH equ 0005h DACCON1_DACR_MASK equ 001Fh DACCON1_DACR0_POSN equ 0000h DACCON1_DACR0_POSITION equ 0000h DACCON1_DACR0_SIZE equ 0001h DACCON1_DACR0_LENGTH equ 0001h DACCON1_DACR0_MASK equ 0001h DACCON1_DACR1_POSN equ 0001h DACCON1_DACR1_POSITION equ 0001h DACCON1_DACR1_SIZE equ 0001h DACCON1_DACR1_LENGTH equ 0001h DACCON1_DACR1_MASK equ 0002h DACCON1_DACR2_POSN equ 0002h DACCON1_DACR2_POSITION equ 0002h DACCON1_DACR2_SIZE equ 0001h DACCON1_DACR2_LENGTH equ 0001h DACCON1_DACR2_MASK equ 0004h DACCON1_DACR3_POSN equ 0003h DACCON1_DACR3_POSITION equ 0003h DACCON1_DACR3_SIZE equ 0001h DACCON1_DACR3_LENGTH equ 0001h DACCON1_DACR3_MASK equ 0008h DACCON1_DACR4_POSN equ 0004h DACCON1_DACR4_POSITION equ 0004h DACCON1_DACR4_SIZE equ 0001h DACCON1_DACR4_LENGTH equ 0001h DACCON1_DACR4_MASK equ 0010h // Register: APFCON APFCON equ 011Dh // bitfield definitions APFCON_P2SEL_POSN equ 0002h APFCON_P2SEL_POSITION equ 0002h APFCON_P2SEL_SIZE equ 0001h APFCON_P2SEL_LENGTH equ 0001h APFCON_P2SEL_MASK equ 0004h APFCON_T1GSEL_POSN equ 0003h APFCON_T1GSEL_POSITION equ 0003h APFCON_T1GSEL_SIZE equ 0001h APFCON_T1GSEL_LENGTH equ 0001h APFCON_T1GSEL_MASK equ 0008h APFCON_SSSEL_POSN equ 0005h APFCON_SSSEL_POSITION equ 0005h APFCON_SSSEL_SIZE equ 0001h APFCON_SSSEL_LENGTH equ 0001h APFCON_SSSEL_MASK equ 0020h APFCON_SDOSEL_POSN equ 0006h APFCON_SDOSEL_POSITION equ 0006h APFCON_SDOSEL_SIZE equ 0001h APFCON_SDOSEL_LENGTH equ 0001h APFCON_SDOSEL_MASK equ 0040h APFCON_CLKRSEL_POSN equ 0007h APFCON_CLKRSEL_POSITION equ 0007h APFCON_CLKRSEL_SIZE equ 0001h APFCON_CLKRSEL_LENGTH equ 0001h APFCON_CLKRSEL_MASK equ 0080h // Register: ANSELA ANSELA equ 018Ch // bitfield definitions ANSELA_ANSA4_POSN equ 0004h ANSELA_ANSA4_POSITION equ 0004h ANSELA_ANSA4_SIZE equ 0001h ANSELA_ANSA4_LENGTH equ 0001h ANSELA_ANSA4_MASK equ 0010h ANSELA_ANSELA_POSN equ 0000h ANSELA_ANSELA_POSITION equ 0000h ANSELA_ANSELA_SIZE equ 0006h ANSELA_ANSELA_LENGTH equ 0006h ANSELA_ANSELA_MASK equ 003Fh // Register: ANSELC ANSELC equ 018Eh // bitfield definitions ANSELC_ANSC0_POSN equ 0000h ANSELC_ANSC0_POSITION equ 0000h ANSELC_ANSC0_SIZE equ 0001h ANSELC_ANSC0_LENGTH equ 0001h ANSELC_ANSC0_MASK equ 0001h ANSELC_ANSC1_POSN equ 0001h ANSELC_ANSC1_POSITION equ 0001h ANSELC_ANSC1_SIZE equ 0001h ANSELC_ANSC1_LENGTH equ 0001h ANSELC_ANSC1_MASK equ 0002h ANSELC_ANSC2_POSN equ 0002h ANSELC_ANSC2_POSITION equ 0002h ANSELC_ANSC2_SIZE equ 0001h ANSELC_ANSC2_LENGTH equ 0001h ANSELC_ANSC2_MASK equ 0004h ANSELC_ANSC3_POSN equ 0003h ANSELC_ANSC3_POSITION equ 0003h ANSELC_ANSC3_SIZE equ 0001h ANSELC_ANSC3_LENGTH equ 0001h ANSELC_ANSC3_MASK equ 0008h ANSELC_ANSELC_POSN equ 0000h ANSELC_ANSELC_POSITION equ 0000h ANSELC_ANSELC_SIZE equ 0008h ANSELC_ANSELC_LENGTH equ 0008h ANSELC_ANSELC_MASK equ 00FFh // Register: PMADRL PMADRL equ 0191h // bitfield definitions PMADRL_PMADRL_POSN equ 0000h PMADRL_PMADRL_POSITION equ 0000h PMADRL_PMADRL_SIZE equ 0008h PMADRL_PMADRL_LENGTH equ 0008h PMADRL_PMADRL_MASK equ 00FFh // Register: PMADRH PMADRH equ 0192h // bitfield definitions PMADRH_PMADRH_POSN equ 0000h PMADRH_PMADRH_POSITION equ 0000h PMADRH_PMADRH_SIZE equ 0007h PMADRH_PMADRH_LENGTH equ 0007h PMADRH_PMADRH_MASK equ 007Fh // Register: PMDATL PMDATL equ 0193h // bitfield definitions PMDATL_PMDATL_POSN equ 0000h PMDATL_PMDATL_POSITION equ 0000h PMDATL_PMDATL_SIZE equ 0008h PMDATL_PMDATL_LENGTH equ 0008h PMDATL_PMDATL_MASK equ 00FFh // Register: PMDATH PMDATH equ 0194h // bitfield definitions PMDATH_PMDATH_POSN equ 0000h PMDATH_PMDATH_POSITION equ 0000h PMDATH_PMDATH_SIZE equ 0006h PMDATH_PMDATH_LENGTH equ 0006h PMDATH_PMDATH_MASK equ 003Fh // Register: PMCON1 PMCON1 equ 0195h // bitfield definitions PMCON1_RD_POSN equ 0000h PMCON1_RD_POSITION equ 0000h PMCON1_RD_SIZE equ 0001h PMCON1_RD_LENGTH equ 0001h PMCON1_RD_MASK equ 0001h PMCON1_WR_POSN equ 0001h PMCON1_WR_POSITION equ 0001h PMCON1_WR_SIZE equ 0001h PMCON1_WR_LENGTH equ 0001h PMCON1_WR_MASK equ 0002h PMCON1_WREN_POSN equ 0002h PMCON1_WREN_POSITION equ 0002h PMCON1_WREN_SIZE equ 0001h PMCON1_WREN_LENGTH equ 0001h PMCON1_WREN_MASK equ 0004h PMCON1_WRERR_POSN equ 0003h PMCON1_WRERR_POSITION equ 0003h PMCON1_WRERR_SIZE equ 0001h PMCON1_WRERR_LENGTH equ 0001h PMCON1_WRERR_MASK equ 0008h PMCON1_FREE_POSN equ 0004h PMCON1_FREE_POSITION equ 0004h PMCON1_FREE_SIZE equ 0001h PMCON1_FREE_LENGTH equ 0001h PMCON1_FREE_MASK equ 0010h PMCON1_LWLO_POSN equ 0005h PMCON1_LWLO_POSITION equ 0005h PMCON1_LWLO_SIZE equ 0001h PMCON1_LWLO_LENGTH equ 0001h PMCON1_LWLO_MASK equ 0020h PMCON1_CFGS_POSN equ 0006h PMCON1_CFGS_POSITION equ 0006h PMCON1_CFGS_SIZE equ 0001h PMCON1_CFGS_LENGTH equ 0001h PMCON1_CFGS_MASK equ 0040h // Register: PMCON2 PMCON2 equ 0196h // bitfield definitions PMCON2_PMCON2_POSN equ 0000h PMCON2_PMCON2_POSITION equ 0000h PMCON2_PMCON2_SIZE equ 0008h PMCON2_PMCON2_LENGTH equ 0008h PMCON2_PMCON2_MASK equ 00FFh // Register: VREGCON VREGCON equ 0197h // bitfield definitions VREGCON_VREGPM_POSN equ 0000h VREGCON_VREGPM_POSITION equ 0000h VREGCON_VREGPM_SIZE equ 0002h VREGCON_VREGPM_LENGTH equ 0002h VREGCON_VREGPM_MASK equ 0003h VREGCON_VREGPM0_POSN equ 0000h VREGCON_VREGPM0_POSITION equ 0000h VREGCON_VREGPM0_SIZE equ 0001h VREGCON_VREGPM0_LENGTH equ 0001h VREGCON_VREGPM0_MASK equ 0001h VREGCON_VREGPM1_POSN equ 0001h VREGCON_VREGPM1_POSITION equ 0001h VREGCON_VREGPM1_SIZE equ 0001h VREGCON_VREGPM1_LENGTH equ 0001h VREGCON_VREGPM1_MASK equ 0002h // Register: RCREG RCREG equ 0199h // bitfield definitions RCREG_RCREG_POSN equ 0000h RCREG_RCREG_POSITION equ 0000h RCREG_RCREG_SIZE equ 0008h RCREG_RCREG_LENGTH equ 0008h RCREG_RCREG_MASK equ 00FFh // Register: TXREG TXREG equ 019Ah // bitfield definitions TXREG_TXREG_POSN equ 0000h TXREG_TXREG_POSITION equ 0000h TXREG_TXREG_SIZE equ 0008h TXREG_TXREG_LENGTH equ 0008h TXREG_TXREG_MASK equ 00FFh // Register: SPBRGL SPBRGL equ 019Bh // bitfield definitions SPBRGL_SPBRGL_POSN equ 0000h SPBRGL_SPBRGL_POSITION equ 0000h SPBRGL_SPBRGL_SIZE equ 0008h SPBRGL_SPBRGL_LENGTH equ 0008h SPBRGL_SPBRGL_MASK equ 00FFh // Register: SPBRGH SPBRGH equ 019Ch // bitfield definitions SPBRGH_SPBRGH_POSN equ 0000h SPBRGH_SPBRGH_POSITION equ 0000h SPBRGH_SPBRGH_SIZE equ 0008h SPBRGH_SPBRGH_LENGTH equ 0008h SPBRGH_SPBRGH_MASK equ 00FFh // Register: RCSTA RCSTA equ 019Dh // bitfield definitions RCSTA_RX9D_POSN equ 0000h RCSTA_RX9D_POSITION equ 0000h RCSTA_RX9D_SIZE equ 0001h RCSTA_RX9D_LENGTH equ 0001h RCSTA_RX9D_MASK equ 0001h RCSTA_OERR_POSN equ 0001h RCSTA_OERR_POSITION equ 0001h RCSTA_OERR_SIZE equ 0001h RCSTA_OERR_LENGTH equ 0001h RCSTA_OERR_MASK equ 0002h RCSTA_FERR_POSN equ 0002h RCSTA_FERR_POSITION equ 0002h RCSTA_FERR_SIZE equ 0001h RCSTA_FERR_LENGTH equ 0001h RCSTA_FERR_MASK equ 0004h RCSTA_ADDEN_POSN equ 0003h RCSTA_ADDEN_POSITION equ 0003h RCSTA_ADDEN_SIZE equ 0001h RCSTA_ADDEN_LENGTH equ 0001h RCSTA_ADDEN_MASK equ 0008h RCSTA_CREN_POSN equ 0004h RCSTA_CREN_POSITION equ 0004h RCSTA_CREN_SIZE equ 0001h RCSTA_CREN_LENGTH equ 0001h RCSTA_CREN_MASK equ 0010h RCSTA_SREN_POSN equ 0005h RCSTA_SREN_POSITION equ 0005h RCSTA_SREN_SIZE equ 0001h RCSTA_SREN_LENGTH equ 0001h RCSTA_SREN_MASK equ 0020h RCSTA_RX9_POSN equ 0006h RCSTA_RX9_POSITION equ 0006h RCSTA_RX9_SIZE equ 0001h RCSTA_RX9_LENGTH equ 0001h RCSTA_RX9_MASK equ 0040h RCSTA_SPEN_POSN equ 0007h RCSTA_SPEN_POSITION equ 0007h RCSTA_SPEN_SIZE equ 0001h RCSTA_SPEN_LENGTH equ 0001h RCSTA_SPEN_MASK equ 0080h // Register: TXSTA TXSTA equ 019Eh // bitfield definitions TXSTA_TX9D_POSN equ 0000h TXSTA_TX9D_POSITION equ 0000h TXSTA_TX9D_SIZE equ 0001h TXSTA_TX9D_LENGTH equ 0001h TXSTA_TX9D_MASK equ 0001h TXSTA_TRMT_POSN equ 0001h TXSTA_TRMT_POSITION equ 0001h TXSTA_TRMT_SIZE equ 0001h TXSTA_TRMT_LENGTH equ 0001h TXSTA_TRMT_MASK equ 0002h TXSTA_BRGH_POSN equ 0002h TXSTA_BRGH_POSITION equ 0002h TXSTA_BRGH_SIZE equ 0001h TXSTA_BRGH_LENGTH equ 0001h TXSTA_BRGH_MASK equ 0004h TXSTA_SENDB_POSN equ 0003h TXSTA_SENDB_POSITION equ 0003h TXSTA_SENDB_SIZE equ 0001h TXSTA_SENDB_LENGTH equ 0001h TXSTA_SENDB_MASK equ 0008h TXSTA_SYNC_POSN equ 0004h TXSTA_SYNC_POSITION equ 0004h TXSTA_SYNC_SIZE equ 0001h TXSTA_SYNC_LENGTH equ 0001h TXSTA_SYNC_MASK equ 0010h TXSTA_TXEN_POSN equ 0005h TXSTA_TXEN_POSITION equ 0005h TXSTA_TXEN_SIZE equ 0001h TXSTA_TXEN_LENGTH equ 0001h TXSTA_TXEN_MASK equ 0020h TXSTA_TX9_POSN equ 0006h TXSTA_TX9_POSITION equ 0006h TXSTA_TX9_SIZE equ 0001h TXSTA_TX9_LENGTH equ 0001h TXSTA_TX9_MASK equ 0040h TXSTA_CSRC_POSN equ 0007h TXSTA_CSRC_POSITION equ 0007h TXSTA_CSRC_SIZE equ 0001h TXSTA_CSRC_LENGTH equ 0001h TXSTA_CSRC_MASK equ 0080h // Register: BAUDCON BAUDCON equ 019Fh // bitfield definitions BAUDCON_ABDEN_POSN equ 0000h BAUDCON_ABDEN_POSITION equ 0000h BAUDCON_ABDEN_SIZE equ 0001h BAUDCON_ABDEN_LENGTH equ 0001h BAUDCON_ABDEN_MASK equ 0001h BAUDCON_WUE_POSN equ 0001h BAUDCON_WUE_POSITION equ 0001h BAUDCON_WUE_SIZE equ 0001h BAUDCON_WUE_LENGTH equ 0001h BAUDCON_WUE_MASK equ 0002h BAUDCON_BRG16_POSN equ 0003h BAUDCON_BRG16_POSITION equ 0003h BAUDCON_BRG16_SIZE equ 0001h BAUDCON_BRG16_LENGTH equ 0001h BAUDCON_BRG16_MASK equ 0008h BAUDCON_SCKP_POSN equ 0004h BAUDCON_SCKP_POSITION equ 0004h BAUDCON_SCKP_SIZE equ 0001h BAUDCON_SCKP_LENGTH equ 0001h BAUDCON_SCKP_MASK equ 0010h BAUDCON_RCIDL_POSN equ 0006h BAUDCON_RCIDL_POSITION equ 0006h BAUDCON_RCIDL_SIZE equ 0001h BAUDCON_RCIDL_LENGTH equ 0001h BAUDCON_RCIDL_MASK equ 0040h BAUDCON_ABDOVF_POSN equ 0007h BAUDCON_ABDOVF_POSITION equ 0007h BAUDCON_ABDOVF_SIZE equ 0001h BAUDCON_ABDOVF_LENGTH equ 0001h BAUDCON_ABDOVF_MASK equ 0080h // Register: WPUA WPUA equ 020Ch // bitfield definitions WPUA_WPUA3_POSN equ 0003h WPUA_WPUA3_POSITION equ 0003h WPUA_WPUA3_SIZE equ 0001h WPUA_WPUA3_LENGTH equ 0001h WPUA_WPUA3_MASK equ 0008h WPUA_WPUA4_POSN equ 0004h WPUA_WPUA4_POSITION equ 0004h WPUA_WPUA4_SIZE equ 0001h WPUA_WPUA4_LENGTH equ 0001h WPUA_WPUA4_MASK equ 0010h WPUA_WPUA5_POSN equ 0005h WPUA_WPUA5_POSITION equ 0005h WPUA_WPUA5_SIZE equ 0001h WPUA_WPUA5_LENGTH equ 0001h WPUA_WPUA5_MASK equ 0020h WPUA_WPUA_POSN equ 0000h WPUA_WPUA_POSITION equ 0000h WPUA_WPUA_SIZE equ 0006h WPUA_WPUA_LENGTH equ 0006h WPUA_WPUA_MASK equ 003Fh // Register: SSP1BUF SSP1BUF equ 0211h // bitfield definitions SSP1BUF_SSPBUF_POSN equ 0000h SSP1BUF_SSPBUF_POSITION equ 0000h SSP1BUF_SSPBUF_SIZE equ 0008h SSP1BUF_SSPBUF_LENGTH equ 0008h SSP1BUF_SSPBUF_MASK equ 00FFh // Register: SSP1ADD SSP1ADD equ 0212h // bitfield definitions SSP1ADD_SSPADD_POSN equ 0000h SSP1ADD_SSPADD_POSITION equ 0000h SSP1ADD_SSPADD_SIZE equ 0008h SSP1ADD_SSPADD_LENGTH equ 0008h SSP1ADD_SSPADD_MASK equ 00FFh // Register: SSP1MSK SSP1MSK equ 0213h // bitfield definitions SSP1MSK_SSPMSK_POSN equ 0000h SSP1MSK_SSPMSK_POSITION equ 0000h SSP1MSK_SSPMSK_SIZE equ 0008h SSP1MSK_SSPMSK_LENGTH equ 0008h SSP1MSK_SSPMSK_MASK equ 00FFh // Register: SSP1STAT SSP1STAT equ 0214h // bitfield definitions SSP1STAT_BF_POSN equ 0000h SSP1STAT_BF_POSITION equ 0000h SSP1STAT_BF_SIZE equ 0001h SSP1STAT_BF_LENGTH equ 0001h SSP1STAT_BF_MASK equ 0001h SSP1STAT_UA_POSN equ 0001h SSP1STAT_UA_POSITION equ 0001h SSP1STAT_UA_SIZE equ 0001h SSP1STAT_UA_LENGTH equ 0001h SSP1STAT_UA_MASK equ 0002h SSP1STAT_R_nW_POSN equ 0002h SSP1STAT_R_nW_POSITION equ 0002h SSP1STAT_R_nW_SIZE equ 0001h SSP1STAT_R_nW_LENGTH equ 0001h SSP1STAT_R_nW_MASK equ 0004h SSP1STAT_S_POSN equ 0003h SSP1STAT_S_POSITION equ 0003h SSP1STAT_S_SIZE equ 0001h SSP1STAT_S_LENGTH equ 0001h SSP1STAT_S_MASK equ 0008h SSP1STAT_P_POSN equ 0004h SSP1STAT_P_POSITION equ 0004h SSP1STAT_P_SIZE equ 0001h SSP1STAT_P_LENGTH equ 0001h SSP1STAT_P_MASK equ 0010h SSP1STAT_D_nA_POSN equ 0005h SSP1STAT_D_nA_POSITION equ 0005h SSP1STAT_D_nA_SIZE equ 0001h SSP1STAT_D_nA_LENGTH equ 0001h SSP1STAT_D_nA_MASK equ 0020h SSP1STAT_CKE_POSN equ 0006h SSP1STAT_CKE_POSITION equ 0006h SSP1STAT_CKE_SIZE equ 0001h SSP1STAT_CKE_LENGTH equ 0001h SSP1STAT_CKE_MASK equ 0040h SSP1STAT_SMP_POSN equ 0007h SSP1STAT_SMP_POSITION equ 0007h SSP1STAT_SMP_SIZE equ 0001h SSP1STAT_SMP_LENGTH equ 0001h SSP1STAT_SMP_MASK equ 0080h // Register: SSP1CON1 SSP1CON1 equ 0215h // bitfield definitions SSP1CON1_SSP1M0_POSN equ 0000h SSP1CON1_SSP1M0_POSITION equ 0000h SSP1CON1_SSP1M0_SIZE equ 0001h SSP1CON1_SSP1M0_LENGTH equ 0001h SSP1CON1_SSP1M0_MASK equ 0001h SSP1CON1_SSP1M1_POSN equ 0001h SSP1CON1_SSP1M1_POSITION equ 0001h SSP1CON1_SSP1M1_SIZE equ 0001h SSP1CON1_SSP1M1_LENGTH equ 0001h SSP1CON1_SSP1M1_MASK equ 0002h SSP1CON1_SSP1M2_POSN equ 0002h SSP1CON1_SSP1M2_POSITION equ 0002h SSP1CON1_SSP1M2_SIZE equ 0001h SSP1CON1_SSP1M2_LENGTH equ 0001h SSP1CON1_SSP1M2_MASK equ 0004h SSP1CON1_SSP1M3_POSN equ 0003h SSP1CON1_SSP1M3_POSITION equ 0003h SSP1CON1_SSP1M3_SIZE equ 0001h SSP1CON1_SSP1M3_LENGTH equ 0001h SSP1CON1_SSP1M3_MASK equ 0008h SSP1CON1_CKP_POSN equ 0004h SSP1CON1_CKP_POSITION equ 0004h SSP1CON1_CKP_SIZE equ 0001h SSP1CON1_CKP_LENGTH equ 0001h SSP1CON1_CKP_MASK equ 0010h SSP1CON1_SSPEN_POSN equ 0005h SSP1CON1_SSPEN_POSITION equ 0005h SSP1CON1_SSPEN_SIZE equ 0001h SSP1CON1_SSPEN_LENGTH equ 0001h SSP1CON1_SSPEN_MASK equ 0020h SSP1CON1_SSPOV_POSN equ 0006h SSP1CON1_SSPOV_POSITION equ 0006h SSP1CON1_SSPOV_SIZE equ 0001h SSP1CON1_SSPOV_LENGTH equ 0001h SSP1CON1_SSPOV_MASK equ 0040h SSP1CON1_WCOL_POSN equ 0007h SSP1CON1_WCOL_POSITION equ 0007h SSP1CON1_WCOL_SIZE equ 0001h SSP1CON1_WCOL_LENGTH equ 0001h SSP1CON1_WCOL_MASK equ 0080h SSP1CON1_SSPM_POSN equ 0000h SSP1CON1_SSPM_POSITION equ 0000h SSP1CON1_SSPM_SIZE equ 0004h SSP1CON1_SSPM_LENGTH equ 0004h SSP1CON1_SSPM_MASK equ 000Fh SSP1CON1_SSP1EN_POSN equ 0005h SSP1CON1_SSP1EN_POSITION equ 0005h SSP1CON1_SSP1EN_SIZE equ 0001h SSP1CON1_SSP1EN_LENGTH equ 0001h SSP1CON1_SSP1EN_MASK equ 0020h SSP1CON1_SSP1OV_POSN equ 0006h SSP1CON1_SSP1OV_POSITION equ 0006h SSP1CON1_SSP1OV_SIZE equ 0001h SSP1CON1_SSP1OV_LENGTH equ 0001h SSP1CON1_SSP1OV_MASK equ 0040h // Register: SSP1CON2 SSP1CON2 equ 0216h // bitfield definitions SSP1CON2_SEN_POSN equ 0000h SSP1CON2_SEN_POSITION equ 0000h SSP1CON2_SEN_SIZE equ 0001h SSP1CON2_SEN_LENGTH equ 0001h SSP1CON2_SEN_MASK equ 0001h SSP1CON2_RSEN_POSN equ 0001h SSP1CON2_RSEN_POSITION equ 0001h SSP1CON2_RSEN_SIZE equ 0001h SSP1CON2_RSEN_LENGTH equ 0001h SSP1CON2_RSEN_MASK equ 0002h SSP1CON2_PEN_POSN equ 0002h SSP1CON2_PEN_POSITION equ 0002h SSP1CON2_PEN_SIZE equ 0001h SSP1CON2_PEN_LENGTH equ 0001h SSP1CON2_PEN_MASK equ 0004h SSP1CON2_RCEN_POSN equ 0003h SSP1CON2_RCEN_POSITION equ 0003h SSP1CON2_RCEN_SIZE equ 0001h SSP1CON2_RCEN_LENGTH equ 0001h SSP1CON2_RCEN_MASK equ 0008h SSP1CON2_ACKEN_POSN equ 0004h SSP1CON2_ACKEN_POSITION equ 0004h SSP1CON2_ACKEN_SIZE equ 0001h SSP1CON2_ACKEN_LENGTH equ 0001h SSP1CON2_ACKEN_MASK equ 0010h SSP1CON2_ACKDT_POSN equ 0005h SSP1CON2_ACKDT_POSITION equ 0005h SSP1CON2_ACKDT_SIZE equ 0001h SSP1CON2_ACKDT_LENGTH equ 0001h SSP1CON2_ACKDT_MASK equ 0020h SSP1CON2_ACKSTAT_POSN equ 0006h SSP1CON2_ACKSTAT_POSITION equ 0006h SSP1CON2_ACKSTAT_SIZE equ 0001h SSP1CON2_ACKSTAT_LENGTH equ 0001h SSP1CON2_ACKSTAT_MASK equ 0040h SSP1CON2_GCEN_POSN equ 0007h SSP1CON2_GCEN_POSITION equ 0007h SSP1CON2_GCEN_SIZE equ 0001h SSP1CON2_GCEN_LENGTH equ 0001h SSP1CON2_GCEN_MASK equ 0080h // Register: SSP1CON3 SSP1CON3 equ 0217h // bitfield definitions SSP1CON3_DHEN_POSN equ 0000h SSP1CON3_DHEN_POSITION equ 0000h SSP1CON3_DHEN_SIZE equ 0001h SSP1CON3_DHEN_LENGTH equ 0001h SSP1CON3_DHEN_MASK equ 0001h SSP1CON3_AHEN_POSN equ 0001h SSP1CON3_AHEN_POSITION equ 0001h SSP1CON3_AHEN_SIZE equ 0001h SSP1CON3_AHEN_LENGTH equ 0001h SSP1CON3_AHEN_MASK equ 0002h SSP1CON3_SBCDE_POSN equ 0002h SSP1CON3_SBCDE_POSITION equ 0002h SSP1CON3_SBCDE_SIZE equ 0001h SSP1CON3_SBCDE_LENGTH equ 0001h SSP1CON3_SBCDE_MASK equ 0004h SSP1CON3_SDAHT_POSN equ 0003h SSP1CON3_SDAHT_POSITION equ 0003h SSP1CON3_SDAHT_SIZE equ 0001h SSP1CON3_SDAHT_LENGTH equ 0001h SSP1CON3_SDAHT_MASK equ 0008h SSP1CON3_BOEN_POSN equ 0004h SSP1CON3_BOEN_POSITION equ 0004h SSP1CON3_BOEN_SIZE equ 0001h SSP1CON3_BOEN_LENGTH equ 0001h SSP1CON3_BOEN_MASK equ 0010h SSP1CON3_SCIE_POSN equ 0005h SSP1CON3_SCIE_POSITION equ 0005h SSP1CON3_SCIE_SIZE equ 0001h SSP1CON3_SCIE_LENGTH equ 0001h SSP1CON3_SCIE_MASK equ 0020h SSP1CON3_PCIE_POSN equ 0006h SSP1CON3_PCIE_POSITION equ 0006h SSP1CON3_PCIE_SIZE equ 0001h SSP1CON3_PCIE_LENGTH equ 0001h SSP1CON3_PCIE_MASK equ 0040h SSP1CON3_ACKTIM_POSN equ 0007h SSP1CON3_ACKTIM_POSITION equ 0007h SSP1CON3_ACKTIM_SIZE equ 0001h SSP1CON3_ACKTIM_LENGTH equ 0001h SSP1CON3_ACKTIM_MASK equ 0080h // Register: IOCAP IOCAP equ 0391h // bitfield definitions IOCAP_IOCAP0_POSN equ 0000h IOCAP_IOCAP0_POSITION equ 0000h IOCAP_IOCAP0_SIZE equ 0001h IOCAP_IOCAP0_LENGTH equ 0001h IOCAP_IOCAP0_MASK equ 0001h IOCAP_IOCAP1_POSN equ 0001h IOCAP_IOCAP1_POSITION equ 0001h IOCAP_IOCAP1_SIZE equ 0001h IOCAP_IOCAP1_LENGTH equ 0001h IOCAP_IOCAP1_MASK equ 0002h IOCAP_IOCAP3_POSN equ 0003h IOCAP_IOCAP3_POSITION equ 0003h IOCAP_IOCAP3_SIZE equ 0001h IOCAP_IOCAP3_LENGTH equ 0001h IOCAP_IOCAP3_MASK equ 0008h IOCAP_IOCAP4_POSN equ 0004h IOCAP_IOCAP4_POSITION equ 0004h IOCAP_IOCAP4_SIZE equ 0001h IOCAP_IOCAP4_LENGTH equ 0001h IOCAP_IOCAP4_MASK equ 0010h IOCAP_IOCAP5_POSN equ 0005h IOCAP_IOCAP5_POSITION equ 0005h IOCAP_IOCAP5_SIZE equ 0001h IOCAP_IOCAP5_LENGTH equ 0001h IOCAP_IOCAP5_MASK equ 0020h IOCAP_IOCAP_POSN equ 0000h IOCAP_IOCAP_POSITION equ 0000h IOCAP_IOCAP_SIZE equ 0006h IOCAP_IOCAP_LENGTH equ 0006h IOCAP_IOCAP_MASK equ 003Fh // Register: IOCAN IOCAN equ 0392h // bitfield definitions IOCAN_IOCAN0_POSN equ 0000h IOCAN_IOCAN0_POSITION equ 0000h IOCAN_IOCAN0_SIZE equ 0001h IOCAN_IOCAN0_LENGTH equ 0001h IOCAN_IOCAN0_MASK equ 0001h IOCAN_IOCAN1_POSN equ 0001h IOCAN_IOCAN1_POSITION equ 0001h IOCAN_IOCAN1_SIZE equ 0001h IOCAN_IOCAN1_LENGTH equ 0001h IOCAN_IOCAN1_MASK equ 0002h IOCAN_IOCAN3_POSN equ 0003h IOCAN_IOCAN3_POSITION equ 0003h IOCAN_IOCAN3_SIZE equ 0001h IOCAN_IOCAN3_LENGTH equ 0001h IOCAN_IOCAN3_MASK equ 0008h IOCAN_IOCAN4_POSN equ 0004h IOCAN_IOCAN4_POSITION equ 0004h IOCAN_IOCAN4_SIZE equ 0001h IOCAN_IOCAN4_LENGTH equ 0001h IOCAN_IOCAN4_MASK equ 0010h IOCAN_IOCAN5_POSN equ 0005h IOCAN_IOCAN5_POSITION equ 0005h IOCAN_IOCAN5_SIZE equ 0001h IOCAN_IOCAN5_LENGTH equ 0001h IOCAN_IOCAN5_MASK equ 0020h IOCAN_IOCAN_POSN equ 0000h IOCAN_IOCAN_POSITION equ 0000h IOCAN_IOCAN_SIZE equ 0006h IOCAN_IOCAN_LENGTH equ 0006h IOCAN_IOCAN_MASK equ 003Fh // Register: IOCAF IOCAF equ 0393h // bitfield definitions IOCAF_IOCAF0_POSN equ 0000h IOCAF_IOCAF0_POSITION equ 0000h IOCAF_IOCAF0_SIZE equ 0001h IOCAF_IOCAF0_LENGTH equ 0001h IOCAF_IOCAF0_MASK equ 0001h IOCAF_IOCAF1_POSN equ 0001h IOCAF_IOCAF1_POSITION equ 0001h IOCAF_IOCAF1_SIZE equ 0001h IOCAF_IOCAF1_LENGTH equ 0001h IOCAF_IOCAF1_MASK equ 0002h IOCAF_IOCAF3_POSN equ 0003h IOCAF_IOCAF3_POSITION equ 0003h IOCAF_IOCAF3_SIZE equ 0001h IOCAF_IOCAF3_LENGTH equ 0001h IOCAF_IOCAF3_MASK equ 0008h IOCAF_IOCAF4_POSN equ 0004h IOCAF_IOCAF4_POSITION equ 0004h IOCAF_IOCAF4_SIZE equ 0001h IOCAF_IOCAF4_LENGTH equ 0001h IOCAF_IOCAF4_MASK equ 0010h IOCAF_IOCAF5_POSN equ 0005h IOCAF_IOCAF5_POSITION equ 0005h IOCAF_IOCAF5_SIZE equ 0001h IOCAF_IOCAF5_LENGTH equ 0001h IOCAF_IOCAF5_MASK equ 0020h IOCAF_IOCAF_POSN equ 0000h IOCAF_IOCAF_POSITION equ 0000h IOCAF_IOCAF_SIZE equ 0006h IOCAF_IOCAF_LENGTH equ 0006h IOCAF_IOCAF_MASK equ 003Fh // Register: CLKRCON CLKRCON equ 039Ah // bitfield definitions CLKRCON_CLKRDIV_POSN equ 0000h CLKRCON_CLKRDIV_POSITION equ 0000h CLKRCON_CLKRDIV_SIZE equ 0003h CLKRCON_CLKRDIV_LENGTH equ 0003h CLKRCON_CLKRDIV_MASK equ 0007h CLKRCON_CLKRCD_POSN equ 0003h CLKRCON_CLKRCD_POSITION equ 0003h CLKRCON_CLKRCD_SIZE equ 0002h CLKRCON_CLKRCD_LENGTH equ 0002h CLKRCON_CLKRCD_MASK equ 0018h CLKRCON_CLKRSLR_POSN equ 0005h CLKRCON_CLKRSLR_POSITION equ 0005h CLKRCON_CLKRSLR_SIZE equ 0001h CLKRCON_CLKRSLR_LENGTH equ 0001h CLKRCON_CLKRSLR_MASK equ 0020h CLKRCON_CLKROE_POSN equ 0006h CLKRCON_CLKROE_POSITION equ 0006h CLKRCON_CLKROE_SIZE equ 0001h CLKRCON_CLKROE_LENGTH equ 0001h CLKRCON_CLKROE_MASK equ 0040h CLKRCON_CLKREN_POSN equ 0007h CLKRCON_CLKREN_POSITION equ 0007h CLKRCON_CLKREN_SIZE equ 0001h CLKRCON_CLKREN_LENGTH equ 0001h CLKRCON_CLKREN_MASK equ 0080h CLKRCON_CLKRDIV0_POSN equ 0000h CLKRCON_CLKRDIV0_POSITION equ 0000h CLKRCON_CLKRDIV0_SIZE equ 0001h CLKRCON_CLKRDIV0_LENGTH equ 0001h CLKRCON_CLKRDIV0_MASK equ 0001h CLKRCON_CLKRDIV1_POSN equ 0001h CLKRCON_CLKRDIV1_POSITION equ 0001h CLKRCON_CLKRDIV1_SIZE equ 0001h CLKRCON_CLKRDIV1_LENGTH equ 0001h CLKRCON_CLKRDIV1_MASK equ 0002h CLKRCON_CLKRDIV2_POSN equ 0002h CLKRCON_CLKRDIV2_POSITION equ 0002h CLKRCON_CLKRDIV2_SIZE equ 0001h CLKRCON_CLKRDIV2_LENGTH equ 0001h CLKRCON_CLKRDIV2_MASK equ 0004h CLKRCON_CLKRCD0_POSN equ 0003h CLKRCON_CLKRCD0_POSITION equ 0003h CLKRCON_CLKRCD0_SIZE equ 0001h CLKRCON_CLKRCD0_LENGTH equ 0001h CLKRCON_CLKRCD0_MASK equ 0008h CLKRCON_CLKRCD1_POSN equ 0004h CLKRCON_CLKRCD1_POSITION equ 0004h CLKRCON_CLKRCD1_SIZE equ 0001h CLKRCON_CLKRCD1_LENGTH equ 0001h CLKRCON_CLKRCD1_MASK equ 0010h // Register: ACTCON ACTCON equ 039Bh // bitfield definitions ACTCON_ACTORS_POSN equ 0001h ACTCON_ACTORS_POSITION equ 0001h ACTCON_ACTORS_SIZE equ 0001h ACTCON_ACTORS_LENGTH equ 0001h ACTCON_ACTORS_MASK equ 0002h ACTCON_ACTLOCK_POSN equ 0003h ACTCON_ACTLOCK_POSITION equ 0003h ACTCON_ACTLOCK_SIZE equ 0001h ACTCON_ACTLOCK_LENGTH equ 0001h ACTCON_ACTLOCK_MASK equ 0008h ACTCON_ACTSRC_POSN equ 0004h ACTCON_ACTSRC_POSITION equ 0004h ACTCON_ACTSRC_SIZE equ 0001h ACTCON_ACTSRC_LENGTH equ 0001h ACTCON_ACTSRC_MASK equ 0010h ACTCON_ACTUD_POSN equ 0006h ACTCON_ACTUD_POSITION equ 0006h ACTCON_ACTUD_SIZE equ 0001h ACTCON_ACTUD_LENGTH equ 0001h ACTCON_ACTUD_MASK equ 0040h ACTCON_ACTEN_POSN equ 0007h ACTCON_ACTEN_POSITION equ 0007h ACTCON_ACTEN_SIZE equ 0001h ACTCON_ACTEN_LENGTH equ 0001h ACTCON_ACTEN_MASK equ 0080h // Register: PWM1DCL PWM1DCL equ 0611h // bitfield definitions PWM1DCL_PWM1DCL_POSN equ 0006h PWM1DCL_PWM1DCL_POSITION equ 0006h PWM1DCL_PWM1DCL_SIZE equ 0002h PWM1DCL_PWM1DCL_LENGTH equ 0002h PWM1DCL_PWM1DCL_MASK equ 00C0h PWM1DCL_PWM1DCL0_POSN equ 0006h PWM1DCL_PWM1DCL0_POSITION equ 0006h PWM1DCL_PWM1DCL0_SIZE equ 0001h PWM1DCL_PWM1DCL0_LENGTH equ 0001h PWM1DCL_PWM1DCL0_MASK equ 0040h PWM1DCL_PWM1DCL1_POSN equ 0007h PWM1DCL_PWM1DCL1_POSITION equ 0007h PWM1DCL_PWM1DCL1_SIZE equ 0001h PWM1DCL_PWM1DCL1_LENGTH equ 0001h PWM1DCL_PWM1DCL1_MASK equ 0080h // Register: PWM1DCH PWM1DCH equ 0612h // bitfield definitions PWM1DCH_PWM1DCH_POSN equ 0000h PWM1DCH_PWM1DCH_POSITION equ 0000h PWM1DCH_PWM1DCH_SIZE equ 0008h PWM1DCH_PWM1DCH_LENGTH equ 0008h PWM1DCH_PWM1DCH_MASK equ 00FFh PWM1DCH_PWM1DCH0_POSN equ 0000h PWM1DCH_PWM1DCH0_POSITION equ 0000h PWM1DCH_PWM1DCH0_SIZE equ 0001h PWM1DCH_PWM1DCH0_LENGTH equ 0001h PWM1DCH_PWM1DCH0_MASK equ 0001h PWM1DCH_PWM1DCH1_POSN equ 0001h PWM1DCH_PWM1DCH1_POSITION equ 0001h PWM1DCH_PWM1DCH1_SIZE equ 0001h PWM1DCH_PWM1DCH1_LENGTH equ 0001h PWM1DCH_PWM1DCH1_MASK equ 0002h PWM1DCH_PWM1DCH2_POSN equ 0002h PWM1DCH_PWM1DCH2_POSITION equ 0002h PWM1DCH_PWM1DCH2_SIZE equ 0001h PWM1DCH_PWM1DCH2_LENGTH equ 0001h PWM1DCH_PWM1DCH2_MASK equ 0004h PWM1DCH_PWM1DCH3_POSN equ 0003h PWM1DCH_PWM1DCH3_POSITION equ 0003h PWM1DCH_PWM1DCH3_SIZE equ 0001h PWM1DCH_PWM1DCH3_LENGTH equ 0001h PWM1DCH_PWM1DCH3_MASK equ 0008h PWM1DCH_PWM1DCH4_POSN equ 0004h PWM1DCH_PWM1DCH4_POSITION equ 0004h PWM1DCH_PWM1DCH4_SIZE equ 0001h PWM1DCH_PWM1DCH4_LENGTH equ 0001h PWM1DCH_PWM1DCH4_MASK equ 0010h PWM1DCH_PWM1DCH5_POSN equ 0005h PWM1DCH_PWM1DCH5_POSITION equ 0005h PWM1DCH_PWM1DCH5_SIZE equ 0001h PWM1DCH_PWM1DCH5_LENGTH equ 0001h PWM1DCH_PWM1DCH5_MASK equ 0020h PWM1DCH_PWM1DCH6_POSN equ 0006h PWM1DCH_PWM1DCH6_POSITION equ 0006h PWM1DCH_PWM1DCH6_SIZE equ 0001h PWM1DCH_PWM1DCH6_LENGTH equ 0001h PWM1DCH_PWM1DCH6_MASK equ 0040h PWM1DCH_PWM1DCH7_POSN equ 0007h PWM1DCH_PWM1DCH7_POSITION equ 0007h PWM1DCH_PWM1DCH7_SIZE equ 0001h PWM1DCH_PWM1DCH7_LENGTH equ 0001h PWM1DCH_PWM1DCH7_MASK equ 0080h // Register: PWM1CON PWM1CON equ 0613h // bitfield definitions PWM1CON_PWM1POL_POSN equ 0004h PWM1CON_PWM1POL_POSITION equ 0004h PWM1CON_PWM1POL_SIZE equ 0001h PWM1CON_PWM1POL_LENGTH equ 0001h PWM1CON_PWM1POL_MASK equ 0010h PWM1CON_PWM1OUT_POSN equ 0005h PWM1CON_PWM1OUT_POSITION equ 0005h PWM1CON_PWM1OUT_SIZE equ 0001h PWM1CON_PWM1OUT_LENGTH equ 0001h PWM1CON_PWM1OUT_MASK equ 0020h PWM1CON_PWM1OE_POSN equ 0006h PWM1CON_PWM1OE_POSITION equ 0006h PWM1CON_PWM1OE_SIZE equ 0001h PWM1CON_PWM1OE_LENGTH equ 0001h PWM1CON_PWM1OE_MASK equ 0040h PWM1CON_PWM1EN_POSN equ 0007h PWM1CON_PWM1EN_POSITION equ 0007h PWM1CON_PWM1EN_SIZE equ 0001h PWM1CON_PWM1EN_LENGTH equ 0001h PWM1CON_PWM1EN_MASK equ 0080h // Register: PWM2DCL PWM2DCL equ 0614h // bitfield definitions PWM2DCL_PWM2DCL_POSN equ 0006h PWM2DCL_PWM2DCL_POSITION equ 0006h PWM2DCL_PWM2DCL_SIZE equ 0002h PWM2DCL_PWM2DCL_LENGTH equ 0002h PWM2DCL_PWM2DCL_MASK equ 00C0h PWM2DCL_PWM2DCL0_POSN equ 0006h PWM2DCL_PWM2DCL0_POSITION equ 0006h PWM2DCL_PWM2DCL0_SIZE equ 0001h PWM2DCL_PWM2DCL0_LENGTH equ 0001h PWM2DCL_PWM2DCL0_MASK equ 0040h PWM2DCL_PWM2DCL1_POSN equ 0007h PWM2DCL_PWM2DCL1_POSITION equ 0007h PWM2DCL_PWM2DCL1_SIZE equ 0001h PWM2DCL_PWM2DCL1_LENGTH equ 0001h PWM2DCL_PWM2DCL1_MASK equ 0080h // Register: PWM2DCH PWM2DCH equ 0615h // bitfield definitions PWM2DCH_PWM2DCH_POSN equ 0000h PWM2DCH_PWM2DCH_POSITION equ 0000h PWM2DCH_PWM2DCH_SIZE equ 0008h PWM2DCH_PWM2DCH_LENGTH equ 0008h PWM2DCH_PWM2DCH_MASK equ 00FFh PWM2DCH_PWM2DCH0_POSN equ 0000h PWM2DCH_PWM2DCH0_POSITION equ 0000h PWM2DCH_PWM2DCH0_SIZE equ 0001h PWM2DCH_PWM2DCH0_LENGTH equ 0001h PWM2DCH_PWM2DCH0_MASK equ 0001h PWM2DCH_PWM2DCH1_POSN equ 0001h PWM2DCH_PWM2DCH1_POSITION equ 0001h PWM2DCH_PWM2DCH1_SIZE equ 0001h PWM2DCH_PWM2DCH1_LENGTH equ 0001h PWM2DCH_PWM2DCH1_MASK equ 0002h PWM2DCH_PWM2DCH2_POSN equ 0002h PWM2DCH_PWM2DCH2_POSITION equ 0002h PWM2DCH_PWM2DCH2_SIZE equ 0001h PWM2DCH_PWM2DCH2_LENGTH equ 0001h PWM2DCH_PWM2DCH2_MASK equ 0004h PWM2DCH_PWM2DCH3_POSN equ 0003h PWM2DCH_PWM2DCH3_POSITION equ 0003h PWM2DCH_PWM2DCH3_SIZE equ 0001h PWM2DCH_PWM2DCH3_LENGTH equ 0001h PWM2DCH_PWM2DCH3_MASK equ 0008h PWM2DCH_PWM2DCH4_POSN equ 0004h PWM2DCH_PWM2DCH4_POSITION equ 0004h PWM2DCH_PWM2DCH4_SIZE equ 0001h PWM2DCH_PWM2DCH4_LENGTH equ 0001h PWM2DCH_PWM2DCH4_MASK equ 0010h PWM2DCH_PWM2DCH5_POSN equ 0005h PWM2DCH_PWM2DCH5_POSITION equ 0005h PWM2DCH_PWM2DCH5_SIZE equ 0001h PWM2DCH_PWM2DCH5_LENGTH equ 0001h PWM2DCH_PWM2DCH5_MASK equ 0020h PWM2DCH_PWM2DCH6_POSN equ 0006h PWM2DCH_PWM2DCH6_POSITION equ 0006h PWM2DCH_PWM2DCH6_SIZE equ 0001h PWM2DCH_PWM2DCH6_LENGTH equ 0001h PWM2DCH_PWM2DCH6_MASK equ 0040h PWM2DCH_PWM2DCH7_POSN equ 0007h PWM2DCH_PWM2DCH7_POSITION equ 0007h PWM2DCH_PWM2DCH7_SIZE equ 0001h PWM2DCH_PWM2DCH7_LENGTH equ 0001h PWM2DCH_PWM2DCH7_MASK equ 0080h // Register: PWM2CON PWM2CON equ 0616h // bitfield definitions PWM2CON_PWM2POL_POSN equ 0004h PWM2CON_PWM2POL_POSITION equ 0004h PWM2CON_PWM2POL_SIZE equ 0001h PWM2CON_PWM2POL_LENGTH equ 0001h PWM2CON_PWM2POL_MASK equ 0010h PWM2CON_PWM2OUT_POSN equ 0005h PWM2CON_PWM2OUT_POSITION equ 0005h PWM2CON_PWM2OUT_SIZE equ 0001h PWM2CON_PWM2OUT_LENGTH equ 0001h PWM2CON_PWM2OUT_MASK equ 0020h PWM2CON_PWM2OE_POSN equ 0006h PWM2CON_PWM2OE_POSITION equ 0006h PWM2CON_PWM2OE_SIZE equ 0001h PWM2CON_PWM2OE_LENGTH equ 0001h PWM2CON_PWM2OE_MASK equ 0040h PWM2CON_PWM2EN_POSN equ 0007h PWM2CON_PWM2EN_POSITION equ 0007h PWM2CON_PWM2EN_SIZE equ 0001h PWM2CON_PWM2EN_LENGTH equ 0001h PWM2CON_PWM2EN_MASK equ 0080h // Register: CWG1DBR CWG1DBR equ 0691h // bitfield definitions CWG1DBR_CWG1DBR_POSN equ 0000h CWG1DBR_CWG1DBR_POSITION equ 0000h CWG1DBR_CWG1DBR_SIZE equ 0006h CWG1DBR_CWG1DBR_LENGTH equ 0006h CWG1DBR_CWG1DBR_MASK equ 003Fh CWG1DBR_CWG1DBR0_POSN equ 0000h CWG1DBR_CWG1DBR0_POSITION equ 0000h CWG1DBR_CWG1DBR0_SIZE equ 0001h CWG1DBR_CWG1DBR0_LENGTH equ 0001h CWG1DBR_CWG1DBR0_MASK equ 0001h CWG1DBR_CWG1DBR1_POSN equ 0001h CWG1DBR_CWG1DBR1_POSITION equ 0001h CWG1DBR_CWG1DBR1_SIZE equ 0001h CWG1DBR_CWG1DBR1_LENGTH equ 0001h CWG1DBR_CWG1DBR1_MASK equ 0002h CWG1DBR_CWG1DBR2_POSN equ 0002h CWG1DBR_CWG1DBR2_POSITION equ 0002h CWG1DBR_CWG1DBR2_SIZE equ 0001h CWG1DBR_CWG1DBR2_LENGTH equ 0001h CWG1DBR_CWG1DBR2_MASK equ 0004h CWG1DBR_CWG1DBR3_POSN equ 0003h CWG1DBR_CWG1DBR3_POSITION equ 0003h CWG1DBR_CWG1DBR3_SIZE equ 0001h CWG1DBR_CWG1DBR3_LENGTH equ 0001h CWG1DBR_CWG1DBR3_MASK equ 0008h CWG1DBR_CWG1DBR4_POSN equ 0004h CWG1DBR_CWG1DBR4_POSITION equ 0004h CWG1DBR_CWG1DBR4_SIZE equ 0001h CWG1DBR_CWG1DBR4_LENGTH equ 0001h CWG1DBR_CWG1DBR4_MASK equ 0010h CWG1DBR_CWG1DBR5_POSN equ 0005h CWG1DBR_CWG1DBR5_POSITION equ 0005h CWG1DBR_CWG1DBR5_SIZE equ 0001h CWG1DBR_CWG1DBR5_LENGTH equ 0001h CWG1DBR_CWG1DBR5_MASK equ 0020h // Register: CWG1DBF CWG1DBF equ 0692h // bitfield definitions CWG1DBF_CWG1DBF_POSN equ 0000h CWG1DBF_CWG1DBF_POSITION equ 0000h CWG1DBF_CWG1DBF_SIZE equ 0006h CWG1DBF_CWG1DBF_LENGTH equ 0006h CWG1DBF_CWG1DBF_MASK equ 003Fh CWG1DBF_CWG1DBF0_POSN equ 0000h CWG1DBF_CWG1DBF0_POSITION equ 0000h CWG1DBF_CWG1DBF0_SIZE equ 0001h CWG1DBF_CWG1DBF0_LENGTH equ 0001h CWG1DBF_CWG1DBF0_MASK equ 0001h CWG1DBF_CWG1DBF1_POSN equ 0001h CWG1DBF_CWG1DBF1_POSITION equ 0001h CWG1DBF_CWG1DBF1_SIZE equ 0001h CWG1DBF_CWG1DBF1_LENGTH equ 0001h CWG1DBF_CWG1DBF1_MASK equ 0002h CWG1DBF_CWG1DBF2_POSN equ 0002h CWG1DBF_CWG1DBF2_POSITION equ 0002h CWG1DBF_CWG1DBF2_SIZE equ 0001h CWG1DBF_CWG1DBF2_LENGTH equ 0001h CWG1DBF_CWG1DBF2_MASK equ 0004h CWG1DBF_CWG1DBF3_POSN equ 0003h CWG1DBF_CWG1DBF3_POSITION equ 0003h CWG1DBF_CWG1DBF3_SIZE equ 0001h CWG1DBF_CWG1DBF3_LENGTH equ 0001h CWG1DBF_CWG1DBF3_MASK equ 0008h CWG1DBF_CWG1DBF4_POSN equ 0004h CWG1DBF_CWG1DBF4_POSITION equ 0004h CWG1DBF_CWG1DBF4_SIZE equ 0001h CWG1DBF_CWG1DBF4_LENGTH equ 0001h CWG1DBF_CWG1DBF4_MASK equ 0010h CWG1DBF_CWG1DBF5_POSN equ 0005h CWG1DBF_CWG1DBF5_POSITION equ 0005h CWG1DBF_CWG1DBF5_SIZE equ 0001h CWG1DBF_CWG1DBF5_LENGTH equ 0001h CWG1DBF_CWG1DBF5_MASK equ 0020h // Register: CWG1CON0 CWG1CON0 equ 0693h // bitfield definitions CWG1CON0_G1CS0_POSN equ 0000h CWG1CON0_G1CS0_POSITION equ 0000h CWG1CON0_G1CS0_SIZE equ 0001h CWG1CON0_G1CS0_LENGTH equ 0001h CWG1CON0_G1CS0_MASK equ 0001h CWG1CON0_G1POLA_POSN equ 0003h CWG1CON0_G1POLA_POSITION equ 0003h CWG1CON0_G1POLA_SIZE equ 0001h CWG1CON0_G1POLA_LENGTH equ 0001h CWG1CON0_G1POLA_MASK equ 0008h CWG1CON0_G1POLB_POSN equ 0004h CWG1CON0_G1POLB_POSITION equ 0004h CWG1CON0_G1POLB_SIZE equ 0001h CWG1CON0_G1POLB_LENGTH equ 0001h CWG1CON0_G1POLB_MASK equ 0010h CWG1CON0_G1OEA_POSN equ 0005h CWG1CON0_G1OEA_POSITION equ 0005h CWG1CON0_G1OEA_SIZE equ 0001h CWG1CON0_G1OEA_LENGTH equ 0001h CWG1CON0_G1OEA_MASK equ 0020h CWG1CON0_G1OEB_POSN equ 0006h CWG1CON0_G1OEB_POSITION equ 0006h CWG1CON0_G1OEB_SIZE equ 0001h CWG1CON0_G1OEB_LENGTH equ 0001h CWG1CON0_G1OEB_MASK equ 0040h CWG1CON0_G1EN_POSN equ 0007h CWG1CON0_G1EN_POSITION equ 0007h CWG1CON0_G1EN_SIZE equ 0001h CWG1CON0_G1EN_LENGTH equ 0001h CWG1CON0_G1EN_MASK equ 0080h CWG1CON0_G1CS_POSN equ 0000h CWG1CON0_G1CS_POSITION equ 0000h CWG1CON0_G1CS_SIZE equ 0002h CWG1CON0_G1CS_LENGTH equ 0002h CWG1CON0_G1CS_MASK equ 0003h // Register: CWG1CON1 CWG1CON1 equ 0694h // bitfield definitions CWG1CON1_G1IS0_POSN equ 0000h CWG1CON1_G1IS0_POSITION equ 0000h CWG1CON1_G1IS0_SIZE equ 0001h CWG1CON1_G1IS0_LENGTH equ 0001h CWG1CON1_G1IS0_MASK equ 0001h CWG1CON1_G1IS1_POSN equ 0001h CWG1CON1_G1IS1_POSITION equ 0001h CWG1CON1_G1IS1_SIZE equ 0001h CWG1CON1_G1IS1_LENGTH equ 0001h CWG1CON1_G1IS1_MASK equ 0002h CWG1CON1_G1ASDLA_POSN equ 0004h CWG1CON1_G1ASDLA_POSITION equ 0004h CWG1CON1_G1ASDLA_SIZE equ 0002h CWG1CON1_G1ASDLA_LENGTH equ 0002h CWG1CON1_G1ASDLA_MASK equ 0030h CWG1CON1_G1ASDLB_POSN equ 0006h CWG1CON1_G1ASDLB_POSITION equ 0006h CWG1CON1_G1ASDLB_SIZE equ 0002h CWG1CON1_G1ASDLB_LENGTH equ 0002h CWG1CON1_G1ASDLB_MASK equ 00C0h CWG1CON1_G1IS_POSN equ 0000h CWG1CON1_G1IS_POSITION equ 0000h CWG1CON1_G1IS_SIZE equ 0004h CWG1CON1_G1IS_LENGTH equ 0004h CWG1CON1_G1IS_MASK equ 000Fh CWG1CON1_G1ASDLA0_POSN equ 0004h CWG1CON1_G1ASDLA0_POSITION equ 0004h CWG1CON1_G1ASDLA0_SIZE equ 0001h CWG1CON1_G1ASDLA0_LENGTH equ 0001h CWG1CON1_G1ASDLA0_MASK equ 0010h CWG1CON1_G1ASDLA1_POSN equ 0005h CWG1CON1_G1ASDLA1_POSITION equ 0005h CWG1CON1_G1ASDLA1_SIZE equ 0001h CWG1CON1_G1ASDLA1_LENGTH equ 0001h CWG1CON1_G1ASDLA1_MASK equ 0020h CWG1CON1_G1ASDLB0_POSN equ 0006h CWG1CON1_G1ASDLB0_POSITION equ 0006h CWG1CON1_G1ASDLB0_SIZE equ 0001h CWG1CON1_G1ASDLB0_LENGTH equ 0001h CWG1CON1_G1ASDLB0_MASK equ 0040h CWG1CON1_G1ASDLB1_POSN equ 0007h CWG1CON1_G1ASDLB1_POSITION equ 0007h CWG1CON1_G1ASDLB1_SIZE equ 0001h CWG1CON1_G1ASDLB1_LENGTH equ 0001h CWG1CON1_G1ASDLB1_MASK equ 0080h // Register: CWG1CON2 CWG1CON2 equ 0695h // bitfield definitions CWG1CON2_G1ASDSFLT_POSN equ 0001h CWG1CON2_G1ASDSFLT_POSITION equ 0001h CWG1CON2_G1ASDSFLT_SIZE equ 0001h CWG1CON2_G1ASDSFLT_LENGTH equ 0001h CWG1CON2_G1ASDSFLT_MASK equ 0002h CWG1CON2_G1ASDSC1_POSN equ 0002h CWG1CON2_G1ASDSC1_POSITION equ 0002h CWG1CON2_G1ASDSC1_SIZE equ 0001h CWG1CON2_G1ASDSC1_LENGTH equ 0001h CWG1CON2_G1ASDSC1_MASK equ 0004h CWG1CON2_G1ASDSC2_POSN equ 0003h CWG1CON2_G1ASDSC2_POSITION equ 0003h CWG1CON2_G1ASDSC2_SIZE equ 0001h CWG1CON2_G1ASDSC2_LENGTH equ 0001h CWG1CON2_G1ASDSC2_MASK equ 0008h CWG1CON2_G1ARSEN_POSN equ 0006h CWG1CON2_G1ARSEN_POSITION equ 0006h CWG1CON2_G1ARSEN_SIZE equ 0001h CWG1CON2_G1ARSEN_LENGTH equ 0001h CWG1CON2_G1ARSEN_MASK equ 0040h CWG1CON2_G1ASE_POSN equ 0007h CWG1CON2_G1ASE_POSITION equ 0007h CWG1CON2_G1ASE_SIZE equ 0001h CWG1CON2_G1ASE_LENGTH equ 0001h CWG1CON2_G1ASE_MASK equ 0080h // Register: UCON UCON equ 0E8Eh // bitfield definitions UCON_SUSPND_POSN equ 0001h UCON_SUSPND_POSITION equ 0001h UCON_SUSPND_SIZE equ 0001h UCON_SUSPND_LENGTH equ 0001h UCON_SUSPND_MASK equ 0002h UCON_RESUME_POSN equ 0002h UCON_RESUME_POSITION equ 0002h UCON_RESUME_SIZE equ 0001h UCON_RESUME_LENGTH equ 0001h UCON_RESUME_MASK equ 0004h UCON_USBEN_POSN equ 0003h UCON_USBEN_POSITION equ 0003h UCON_USBEN_SIZE equ 0001h UCON_USBEN_LENGTH equ 0001h UCON_USBEN_MASK equ 0008h UCON_PKTDIS_POSN equ 0004h UCON_PKTDIS_POSITION equ 0004h UCON_PKTDIS_SIZE equ 0001h UCON_PKTDIS_LENGTH equ 0001h UCON_PKTDIS_MASK equ 0010h UCON_SE0_POSN equ 0005h UCON_SE0_POSITION equ 0005h UCON_SE0_SIZE equ 0001h UCON_SE0_LENGTH equ 0001h UCON_SE0_MASK equ 0020h UCON_PPBRST_POSN equ 0006h UCON_PPBRST_POSITION equ 0006h UCON_PPBRST_SIZE equ 0001h UCON_PPBRST_LENGTH equ 0001h UCON_PPBRST_MASK equ 0040h // Register: USTAT USTAT equ 0E8Fh // bitfield definitions USTAT_PPBI_POSN equ 0001h USTAT_PPBI_POSITION equ 0001h USTAT_PPBI_SIZE equ 0001h USTAT_PPBI_LENGTH equ 0001h USTAT_PPBI_MASK equ 0002h USTAT_DIR_POSN equ 0002h USTAT_DIR_POSITION equ 0002h USTAT_DIR_SIZE equ 0001h USTAT_DIR_LENGTH equ 0001h USTAT_DIR_MASK equ 0004h USTAT_ENDP_POSN equ 0003h USTAT_ENDP_POSITION equ 0003h USTAT_ENDP_SIZE equ 0004h USTAT_ENDP_LENGTH equ 0004h USTAT_ENDP_MASK equ 0078h USTAT_ENDP0_POSN equ 0003h USTAT_ENDP0_POSITION equ 0003h USTAT_ENDP0_SIZE equ 0001h USTAT_ENDP0_LENGTH equ 0001h USTAT_ENDP0_MASK equ 0008h USTAT_ENDP1_POSN equ 0004h USTAT_ENDP1_POSITION equ 0004h USTAT_ENDP1_SIZE equ 0001h USTAT_ENDP1_LENGTH equ 0001h USTAT_ENDP1_MASK equ 0010h USTAT_ENDP2_POSN equ 0005h USTAT_ENDP2_POSITION equ 0005h USTAT_ENDP2_SIZE equ 0001h USTAT_ENDP2_LENGTH equ 0001h USTAT_ENDP2_MASK equ 0020h USTAT_ENDP3_POSN equ 0006h USTAT_ENDP3_POSITION equ 0006h USTAT_ENDP3_SIZE equ 0001h USTAT_ENDP3_LENGTH equ 0001h USTAT_ENDP3_MASK equ 0040h // Register: UIR UIR equ 0E90h // bitfield definitions UIR_URSTIF_POSN equ 0000h UIR_URSTIF_POSITION equ 0000h UIR_URSTIF_SIZE equ 0001h UIR_URSTIF_LENGTH equ 0001h UIR_URSTIF_MASK equ 0001h UIR_UERRIF_POSN equ 0001h UIR_UERRIF_POSITION equ 0001h UIR_UERRIF_SIZE equ 0001h UIR_UERRIF_LENGTH equ 0001h UIR_UERRIF_MASK equ 0002h UIR_ACTVIF_POSN equ 0002h UIR_ACTVIF_POSITION equ 0002h UIR_ACTVIF_SIZE equ 0001h UIR_ACTVIF_LENGTH equ 0001h UIR_ACTVIF_MASK equ 0004h UIR_TRNIF_POSN equ 0003h UIR_TRNIF_POSITION equ 0003h UIR_TRNIF_SIZE equ 0001h UIR_TRNIF_LENGTH equ 0001h UIR_TRNIF_MASK equ 0008h UIR_IDLEIF_POSN equ 0004h UIR_IDLEIF_POSITION equ 0004h UIR_IDLEIF_SIZE equ 0001h UIR_IDLEIF_LENGTH equ 0001h UIR_IDLEIF_MASK equ 0010h UIR_STALLIF_POSN equ 0005h UIR_STALLIF_POSITION equ 0005h UIR_STALLIF_SIZE equ 0001h UIR_STALLIF_LENGTH equ 0001h UIR_STALLIF_MASK equ 0020h UIR_SOFIF_POSN equ 0006h UIR_SOFIF_POSITION equ 0006h UIR_SOFIF_SIZE equ 0001h UIR_SOFIF_LENGTH equ 0001h UIR_SOFIF_MASK equ 0040h // Register: UCFG UCFG equ 0E91h // bitfield definitions UCFG_PPB_POSN equ 0000h UCFG_PPB_POSITION equ 0000h UCFG_PPB_SIZE equ 0002h UCFG_PPB_LENGTH equ 0002h UCFG_PPB_MASK equ 0003h UCFG_FSEN_POSN equ 0002h UCFG_FSEN_POSITION equ 0002h UCFG_FSEN_SIZE equ 0001h UCFG_FSEN_LENGTH equ 0001h UCFG_FSEN_MASK equ 0004h UCFG_UPUEN_POSN equ 0004h UCFG_UPUEN_POSITION equ 0004h UCFG_UPUEN_SIZE equ 0001h UCFG_UPUEN_LENGTH equ 0001h UCFG_UPUEN_MASK equ 0010h UCFG_UTEYE_POSN equ 0007h UCFG_UTEYE_POSITION equ 0007h UCFG_UTEYE_SIZE equ 0001h UCFG_UTEYE_LENGTH equ 0001h UCFG_UTEYE_MASK equ 0080h UCFG_PPB0_POSN equ 0000h UCFG_PPB0_POSITION equ 0000h UCFG_PPB0_SIZE equ 0001h UCFG_PPB0_LENGTH equ 0001h UCFG_PPB0_MASK equ 0001h UCFG_PPB1_POSN equ 0001h UCFG_PPB1_POSITION equ 0001h UCFG_PPB1_SIZE equ 0001h UCFG_PPB1_LENGTH equ 0001h UCFG_PPB1_MASK equ 0002h // Register: UIE UIE equ 0E92h // bitfield definitions UIE_URSTIE_POSN equ 0000h UIE_URSTIE_POSITION equ 0000h UIE_URSTIE_SIZE equ 0001h UIE_URSTIE_LENGTH equ 0001h UIE_URSTIE_MASK equ 0001h UIE_UERRIE_POSN equ 0001h UIE_UERRIE_POSITION equ 0001h UIE_UERRIE_SIZE equ 0001h UIE_UERRIE_LENGTH equ 0001h UIE_UERRIE_MASK equ 0002h UIE_ACTVIE_POSN equ 0002h UIE_ACTVIE_POSITION equ 0002h UIE_ACTVIE_SIZE equ 0001h UIE_ACTVIE_LENGTH equ 0001h UIE_ACTVIE_MASK equ 0004h UIE_TRNIE_POSN equ 0003h UIE_TRNIE_POSITION equ 0003h UIE_TRNIE_SIZE equ 0001h UIE_TRNIE_LENGTH equ 0001h UIE_TRNIE_MASK equ 0008h UIE_IDLEIE_POSN equ 0004h UIE_IDLEIE_POSITION equ 0004h UIE_IDLEIE_SIZE equ 0001h UIE_IDLEIE_LENGTH equ 0001h UIE_IDLEIE_MASK equ 0010h UIE_STALLIE_POSN equ 0005h UIE_STALLIE_POSITION equ 0005h UIE_STALLIE_SIZE equ 0001h UIE_STALLIE_LENGTH equ 0001h UIE_STALLIE_MASK equ 0020h UIE_SOFIE_POSN equ 0006h UIE_SOFIE_POSITION equ 0006h UIE_SOFIE_SIZE equ 0001h UIE_SOFIE_LENGTH equ 0001h UIE_SOFIE_MASK equ 0040h // Register: UEIR UEIR equ 0E93h // bitfield definitions UEIR_PIDEF_POSN equ 0000h UEIR_PIDEF_POSITION equ 0000h UEIR_PIDEF_SIZE equ 0001h UEIR_PIDEF_LENGTH equ 0001h UEIR_PIDEF_MASK equ 0001h UEIR_CRC5EF_POSN equ 0001h UEIR_CRC5EF_POSITION equ 0001h UEIR_CRC5EF_SIZE equ 0001h UEIR_CRC5EF_LENGTH equ 0001h UEIR_CRC5EF_MASK equ 0002h UEIR_CRC16EF_POSN equ 0002h UEIR_CRC16EF_POSITION equ 0002h UEIR_CRC16EF_SIZE equ 0001h UEIR_CRC16EF_LENGTH equ 0001h UEIR_CRC16EF_MASK equ 0004h UEIR_DFN8EF_POSN equ 0003h UEIR_DFN8EF_POSITION equ 0003h UEIR_DFN8EF_SIZE equ 0001h UEIR_DFN8EF_LENGTH equ 0001h UEIR_DFN8EF_MASK equ 0008h UEIR_BTOEF_POSN equ 0004h UEIR_BTOEF_POSITION equ 0004h UEIR_BTOEF_SIZE equ 0001h UEIR_BTOEF_LENGTH equ 0001h UEIR_BTOEF_MASK equ 0010h UEIR_BTSEF_POSN equ 0007h UEIR_BTSEF_POSITION equ 0007h UEIR_BTSEF_SIZE equ 0001h UEIR_BTSEF_LENGTH equ 0001h UEIR_BTSEF_MASK equ 0080h // Register: UFRMH UFRMH equ 0E94h // bitfield definitions UFRMH_FRM8_POSN equ 0000h UFRMH_FRM8_POSITION equ 0000h UFRMH_FRM8_SIZE equ 0001h UFRMH_FRM8_LENGTH equ 0001h UFRMH_FRM8_MASK equ 0001h UFRMH_FRM9_POSN equ 0001h UFRMH_FRM9_POSITION equ 0001h UFRMH_FRM9_SIZE equ 0001h UFRMH_FRM9_LENGTH equ 0001h UFRMH_FRM9_MASK equ 0002h UFRMH_FRM10_POSN equ 0002h UFRMH_FRM10_POSITION equ 0002h UFRMH_FRM10_SIZE equ 0001h UFRMH_FRM10_LENGTH equ 0001h UFRMH_FRM10_MASK equ 0004h // Register: UFRML UFRML equ 0E95h // bitfield definitions UFRML_FRM0_POSN equ 0000h UFRML_FRM0_POSITION equ 0000h UFRML_FRM0_SIZE equ 0001h UFRML_FRM0_LENGTH equ 0001h UFRML_FRM0_MASK equ 0001h UFRML_FRM1_POSN equ 0001h UFRML_FRM1_POSITION equ 0001h UFRML_FRM1_SIZE equ 0001h UFRML_FRM1_LENGTH equ 0001h UFRML_FRM1_MASK equ 0002h UFRML_FRM2_POSN equ 0002h UFRML_FRM2_POSITION equ 0002h UFRML_FRM2_SIZE equ 0001h UFRML_FRM2_LENGTH equ 0001h UFRML_FRM2_MASK equ 0004h UFRML_FRM3_POSN equ 0003h UFRML_FRM3_POSITION equ 0003h UFRML_FRM3_SIZE equ 0001h UFRML_FRM3_LENGTH equ 0001h UFRML_FRM3_MASK equ 0008h UFRML_FRM4_POSN equ 0004h UFRML_FRM4_POSITION equ 0004h UFRML_FRM4_SIZE equ 0001h UFRML_FRM4_LENGTH equ 0001h UFRML_FRM4_MASK equ 0010h UFRML_FRM5_POSN equ 0005h UFRML_FRM5_POSITION equ 0005h UFRML_FRM5_SIZE equ 0001h UFRML_FRM5_LENGTH equ 0001h UFRML_FRM5_MASK equ 0020h UFRML_FRM6_POSN equ 0006h UFRML_FRM6_POSITION equ 0006h UFRML_FRM6_SIZE equ 0001h UFRML_FRM6_LENGTH equ 0001h UFRML_FRM6_MASK equ 0040h UFRML_FRM7_POSN equ 0007h UFRML_FRM7_POSITION equ 0007h UFRML_FRM7_SIZE equ 0001h UFRML_FRM7_LENGTH equ 0001h UFRML_FRM7_MASK equ 0080h // Register: UADDR UADDR equ 0E96h // bitfield definitions UADDR_ADDR0_POSN equ 0000h UADDR_ADDR0_POSITION equ 0000h UADDR_ADDR0_SIZE equ 0001h UADDR_ADDR0_LENGTH equ 0001h UADDR_ADDR0_MASK equ 0001h UADDR_ADDR1_POSN equ 0001h UADDR_ADDR1_POSITION equ 0001h UADDR_ADDR1_SIZE equ 0001h UADDR_ADDR1_LENGTH equ 0001h UADDR_ADDR1_MASK equ 0002h UADDR_ADDR2_POSN equ 0002h UADDR_ADDR2_POSITION equ 0002h UADDR_ADDR2_SIZE equ 0001h UADDR_ADDR2_LENGTH equ 0001h UADDR_ADDR2_MASK equ 0004h UADDR_ADDR3_POSN equ 0003h UADDR_ADDR3_POSITION equ 0003h UADDR_ADDR3_SIZE equ 0001h UADDR_ADDR3_LENGTH equ 0001h UADDR_ADDR3_MASK equ 0008h UADDR_ADDR4_POSN equ 0004h UADDR_ADDR4_POSITION equ 0004h UADDR_ADDR4_SIZE equ 0001h UADDR_ADDR4_LENGTH equ 0001h UADDR_ADDR4_MASK equ 0010h UADDR_ADDR5_POSN equ 0005h UADDR_ADDR5_POSITION equ 0005h UADDR_ADDR5_SIZE equ 0001h UADDR_ADDR5_LENGTH equ 0001h UADDR_ADDR5_MASK equ 0020h UADDR_ADDR6_POSN equ 0006h UADDR_ADDR6_POSITION equ 0006h UADDR_ADDR6_SIZE equ 0001h UADDR_ADDR6_LENGTH equ 0001h UADDR_ADDR6_MASK equ 0040h // Register: UEIE UEIE equ 0E97h // bitfield definitions UEIE_PIDEE_POSN equ 0000h UEIE_PIDEE_POSITION equ 0000h UEIE_PIDEE_SIZE equ 0001h UEIE_PIDEE_LENGTH equ 0001h UEIE_PIDEE_MASK equ 0001h UEIE_CRC5EE_POSN equ 0001h UEIE_CRC5EE_POSITION equ 0001h UEIE_CRC5EE_SIZE equ 0001h UEIE_CRC5EE_LENGTH equ 0001h UEIE_CRC5EE_MASK equ 0002h UEIE_CRC16EE_POSN equ 0002h UEIE_CRC16EE_POSITION equ 0002h UEIE_CRC16EE_SIZE equ 0001h UEIE_CRC16EE_LENGTH equ 0001h UEIE_CRC16EE_MASK equ 0004h UEIE_DFN8EE_POSN equ 0003h UEIE_DFN8EE_POSITION equ 0003h UEIE_DFN8EE_SIZE equ 0001h UEIE_DFN8EE_LENGTH equ 0001h UEIE_DFN8EE_MASK equ 0008h UEIE_BTOEE_POSN equ 0004h UEIE_BTOEE_POSITION equ 0004h UEIE_BTOEE_SIZE equ 0001h UEIE_BTOEE_LENGTH equ 0001h UEIE_BTOEE_MASK equ 0010h UEIE_BTSEE_POSN equ 0007h UEIE_BTSEE_POSITION equ 0007h UEIE_BTSEE_SIZE equ 0001h UEIE_BTSEE_LENGTH equ 0001h UEIE_BTSEE_MASK equ 0080h // Register: UEP0 UEP0 equ 0E98h // bitfield definitions UEP0_EPSTALL_POSN equ 0000h UEP0_EPSTALL_POSITION equ 0000h UEP0_EPSTALL_SIZE equ 0001h UEP0_EPSTALL_LENGTH equ 0001h UEP0_EPSTALL_MASK equ 0001h UEP0_EPINEN_POSN equ 0001h UEP0_EPINEN_POSITION equ 0001h UEP0_EPINEN_SIZE equ 0001h UEP0_EPINEN_LENGTH equ 0001h UEP0_EPINEN_MASK equ 0002h UEP0_EPOUTEN_POSN equ 0002h UEP0_EPOUTEN_POSITION equ 0002h UEP0_EPOUTEN_SIZE equ 0001h UEP0_EPOUTEN_LENGTH equ 0001h UEP0_EPOUTEN_MASK equ 0004h UEP0_EPCONDIS_POSN equ 0003h UEP0_EPCONDIS_POSITION equ 0003h UEP0_EPCONDIS_SIZE equ 0001h UEP0_EPCONDIS_LENGTH equ 0001h UEP0_EPCONDIS_MASK equ 0008h UEP0_EPHSHK_POSN equ 0004h UEP0_EPHSHK_POSITION equ 0004h UEP0_EPHSHK_SIZE equ 0001h UEP0_EPHSHK_LENGTH equ 0001h UEP0_EPHSHK_MASK equ 0010h // Register: UEP1 UEP1 equ 0E99h // bitfield definitions UEP1_EPSTALL_POSN equ 0000h UEP1_EPSTALL_POSITION equ 0000h UEP1_EPSTALL_SIZE equ 0001h UEP1_EPSTALL_LENGTH equ 0001h UEP1_EPSTALL_MASK equ 0001h UEP1_EPINEN_POSN equ 0001h UEP1_EPINEN_POSITION equ 0001h UEP1_EPINEN_SIZE equ 0001h UEP1_EPINEN_LENGTH equ 0001h UEP1_EPINEN_MASK equ 0002h UEP1_EPOUTEN_POSN equ 0002h UEP1_EPOUTEN_POSITION equ 0002h UEP1_EPOUTEN_SIZE equ 0001h UEP1_EPOUTEN_LENGTH equ 0001h UEP1_EPOUTEN_MASK equ 0004h UEP1_EPCONDIS_POSN equ 0003h UEP1_EPCONDIS_POSITION equ 0003h UEP1_EPCONDIS_SIZE equ 0001h UEP1_EPCONDIS_LENGTH equ 0001h UEP1_EPCONDIS_MASK equ 0008h UEP1_EPHSHK_POSN equ 0004h UEP1_EPHSHK_POSITION equ 0004h UEP1_EPHSHK_SIZE equ 0001h UEP1_EPHSHK_LENGTH equ 0001h UEP1_EPHSHK_MASK equ 0010h // Register: UEP2 UEP2 equ 0E9Ah // bitfield definitions UEP2_EPSTALL_POSN equ 0000h UEP2_EPSTALL_POSITION equ 0000h UEP2_EPSTALL_SIZE equ 0001h UEP2_EPSTALL_LENGTH equ 0001h UEP2_EPSTALL_MASK equ 0001h UEP2_EPINEN_POSN equ 0001h UEP2_EPINEN_POSITION equ 0001h UEP2_EPINEN_SIZE equ 0001h UEP2_EPINEN_LENGTH equ 0001h UEP2_EPINEN_MASK equ 0002h UEP2_EPOUTEN_POSN equ 0002h UEP2_EPOUTEN_POSITION equ 0002h UEP2_EPOUTEN_SIZE equ 0001h UEP2_EPOUTEN_LENGTH equ 0001h UEP2_EPOUTEN_MASK equ 0004h UEP2_EPCONDIS_POSN equ 0003h UEP2_EPCONDIS_POSITION equ 0003h UEP2_EPCONDIS_SIZE equ 0001h UEP2_EPCONDIS_LENGTH equ 0001h UEP2_EPCONDIS_MASK equ 0008h UEP2_EPHSHK_POSN equ 0004h UEP2_EPHSHK_POSITION equ 0004h UEP2_EPHSHK_SIZE equ 0001h UEP2_EPHSHK_LENGTH equ 0001h UEP2_EPHSHK_MASK equ 0010h // Register: UEP3 UEP3 equ 0E9Bh // bitfield definitions UEP3_EPSTALL_POSN equ 0000h UEP3_EPSTALL_POSITION equ 0000h UEP3_EPSTALL_SIZE equ 0001h UEP3_EPSTALL_LENGTH equ 0001h UEP3_EPSTALL_MASK equ 0001h UEP3_EPINEN_POSN equ 0001h UEP3_EPINEN_POSITION equ 0001h UEP3_EPINEN_SIZE equ 0001h UEP3_EPINEN_LENGTH equ 0001h UEP3_EPINEN_MASK equ 0002h UEP3_EPOUTEN_POSN equ 0002h UEP3_EPOUTEN_POSITION equ 0002h UEP3_EPOUTEN_SIZE equ 0001h UEP3_EPOUTEN_LENGTH equ 0001h UEP3_EPOUTEN_MASK equ 0004h UEP3_EPCONDIS_POSN equ 0003h UEP3_EPCONDIS_POSITION equ 0003h UEP3_EPCONDIS_SIZE equ 0001h UEP3_EPCONDIS_LENGTH equ 0001h UEP3_EPCONDIS_MASK equ 0008h UEP3_EPHSHK_POSN equ 0004h UEP3_EPHSHK_POSITION equ 0004h UEP3_EPHSHK_SIZE equ 0001h UEP3_EPHSHK_LENGTH equ 0001h UEP3_EPHSHK_MASK equ 0010h // Register: UEP4 UEP4 equ 0E9Ch // bitfield definitions UEP4_EPSTALL_POSN equ 0000h UEP4_EPSTALL_POSITION equ 0000h UEP4_EPSTALL_SIZE equ 0001h UEP4_EPSTALL_LENGTH equ 0001h UEP4_EPSTALL_MASK equ 0001h UEP4_EPINEN_POSN equ 0001h UEP4_EPINEN_POSITION equ 0001h UEP4_EPINEN_SIZE equ 0001h UEP4_EPINEN_LENGTH equ 0001h UEP4_EPINEN_MASK equ 0002h UEP4_EPOUTEN_POSN equ 0002h UEP4_EPOUTEN_POSITION equ 0002h UEP4_EPOUTEN_SIZE equ 0001h UEP4_EPOUTEN_LENGTH equ 0001h UEP4_EPOUTEN_MASK equ 0004h UEP4_EPCONDIS_POSN equ 0003h UEP4_EPCONDIS_POSITION equ 0003h UEP4_EPCONDIS_SIZE equ 0001h UEP4_EPCONDIS_LENGTH equ 0001h UEP4_EPCONDIS_MASK equ 0008h UEP4_EPHSHK_POSN equ 0004h UEP4_EPHSHK_POSITION equ 0004h UEP4_EPHSHK_SIZE equ 0001h UEP4_EPHSHK_LENGTH equ 0001h UEP4_EPHSHK_MASK equ 0010h // Register: UEP5 UEP5 equ 0E9Dh // bitfield definitions UEP5_EPSTALL_POSN equ 0000h UEP5_EPSTALL_POSITION equ 0000h UEP5_EPSTALL_SIZE equ 0001h UEP5_EPSTALL_LENGTH equ 0001h UEP5_EPSTALL_MASK equ 0001h UEP5_EPINEN_POSN equ 0001h UEP5_EPINEN_POSITION equ 0001h UEP5_EPINEN_SIZE equ 0001h UEP5_EPINEN_LENGTH equ 0001h UEP5_EPINEN_MASK equ 0002h UEP5_EPOUTEN_POSN equ 0002h UEP5_EPOUTEN_POSITION equ 0002h UEP5_EPOUTEN_SIZE equ 0001h UEP5_EPOUTEN_LENGTH equ 0001h UEP5_EPOUTEN_MASK equ 0004h UEP5_EPCONDIS_POSN equ 0003h UEP5_EPCONDIS_POSITION equ 0003h UEP5_EPCONDIS_SIZE equ 0001h UEP5_EPCONDIS_LENGTH equ 0001h UEP5_EPCONDIS_MASK equ 0008h UEP5_EPHSHK_POSN equ 0004h UEP5_EPHSHK_POSITION equ 0004h UEP5_EPHSHK_SIZE equ 0001h UEP5_EPHSHK_LENGTH equ 0001h UEP5_EPHSHK_MASK equ 0010h // Register: UEP6 UEP6 equ 0E9Eh // bitfield definitions UEP6_EPSTALL_POSN equ 0000h UEP6_EPSTALL_POSITION equ 0000h UEP6_EPSTALL_SIZE equ 0001h UEP6_EPSTALL_LENGTH equ 0001h UEP6_EPSTALL_MASK equ 0001h UEP6_EPINEN_POSN equ 0001h UEP6_EPINEN_POSITION equ 0001h UEP6_EPINEN_SIZE equ 0001h UEP6_EPINEN_LENGTH equ 0001h UEP6_EPINEN_MASK equ 0002h UEP6_EPOUTEN_POSN equ 0002h UEP6_EPOUTEN_POSITION equ 0002h UEP6_EPOUTEN_SIZE equ 0001h UEP6_EPOUTEN_LENGTH equ 0001h UEP6_EPOUTEN_MASK equ 0004h UEP6_EPCONDIS_POSN equ 0003h UEP6_EPCONDIS_POSITION equ 0003h UEP6_EPCONDIS_SIZE equ 0001h UEP6_EPCONDIS_LENGTH equ 0001h UEP6_EPCONDIS_MASK equ 0008h UEP6_EPHSHK_POSN equ 0004h UEP6_EPHSHK_POSITION equ 0004h UEP6_EPHSHK_SIZE equ 0001h UEP6_EPHSHK_LENGTH equ 0001h UEP6_EPHSHK_MASK equ 0010h // Register: UEP7 UEP7 equ 0E9Fh // bitfield definitions UEP7_EPSTALL_POSN equ 0000h UEP7_EPSTALL_POSITION equ 0000h UEP7_EPSTALL_SIZE equ 0001h UEP7_EPSTALL_LENGTH equ 0001h UEP7_EPSTALL_MASK equ 0001h UEP7_EPINEN_POSN equ 0001h UEP7_EPINEN_POSITION equ 0001h UEP7_EPINEN_SIZE equ 0001h UEP7_EPINEN_LENGTH equ 0001h UEP7_EPINEN_MASK equ 0002h UEP7_EPOUTEN_POSN equ 0002h UEP7_EPOUTEN_POSITION equ 0002h UEP7_EPOUTEN_SIZE equ 0001h UEP7_EPOUTEN_LENGTH equ 0001h UEP7_EPOUTEN_MASK equ 0004h UEP7_EPCONDIS_POSN equ 0003h UEP7_EPCONDIS_POSITION equ 0003h UEP7_EPCONDIS_SIZE equ 0001h UEP7_EPCONDIS_LENGTH equ 0001h UEP7_EPCONDIS_MASK equ 0008h UEP7_EPHSHK_POSN equ 0004h UEP7_EPHSHK_POSITION equ 0004h UEP7_EPHSHK_SIZE equ 0001h UEP7_EPHSHK_LENGTH equ 0001h UEP7_EPHSHK_MASK equ 0010h // Register: STATUS_SHAD STATUS_SHAD equ 0FE4h // bitfield definitions STATUS_SHAD_C_POSN equ 0000h STATUS_SHAD_C_POSITION equ 0000h STATUS_SHAD_C_SIZE equ 0001h STATUS_SHAD_C_LENGTH equ 0001h STATUS_SHAD_C_MASK equ 0001h STATUS_SHAD_DC_POSN equ 0001h STATUS_SHAD_DC_POSITION equ 0001h STATUS_SHAD_DC_SIZE equ 0001h STATUS_SHAD_DC_LENGTH equ 0001h STATUS_SHAD_DC_MASK equ 0002h STATUS_SHAD_Z_POSN equ 0002h STATUS_SHAD_Z_POSITION equ 0002h STATUS_SHAD_Z_SIZE equ 0001h STATUS_SHAD_Z_LENGTH equ 0001h STATUS_SHAD_Z_MASK equ 0004h // Register: WREG_SHAD WREG_SHAD equ 0FE5h // bitfield definitions WREG_SHAD_WREG_SHAD_POSN equ 0000h WREG_SHAD_WREG_SHAD_POSITION equ 0000h WREG_SHAD_WREG_SHAD_SIZE equ 0008h WREG_SHAD_WREG_SHAD_LENGTH equ 0008h WREG_SHAD_WREG_SHAD_MASK equ 00FFh // Register: BSR_SHAD BSR_SHAD equ 0FE6h // bitfield definitions BSR_SHAD_BSR_SHAD_POSN equ 0000h BSR_SHAD_BSR_SHAD_POSITION equ 0000h BSR_SHAD_BSR_SHAD_SIZE equ 0005h BSR_SHAD_BSR_SHAD_LENGTH equ 0005h BSR_SHAD_BSR_SHAD_MASK equ 001Fh // Register: PCLATH_SHAD PCLATH_SHAD equ 0FE7h // bitfield definitions PCLATH_SHAD_PCLATH_SHAD_POSN equ 0000h PCLATH_SHAD_PCLATH_SHAD_POSITION equ 0000h PCLATH_SHAD_PCLATH_SHAD_SIZE equ 0007h PCLATH_SHAD_PCLATH_SHAD_LENGTH equ 0007h PCLATH_SHAD_PCLATH_SHAD_MASK equ 007Fh // Register: FSR0L_SHAD FSR0L_SHAD equ 0FE8h // bitfield definitions FSR0L_SHAD_FSR0L_SHAD_POSN equ 0000h FSR0L_SHAD_FSR0L_SHAD_POSITION equ 0000h FSR0L_SHAD_FSR0L_SHAD_SIZE equ 0008h FSR0L_SHAD_FSR0L_SHAD_LENGTH equ 0008h FSR0L_SHAD_FSR0L_SHAD_MASK equ 00FFh // Register: FSR0H_SHAD FSR0H_SHAD equ 0FE9h // bitfield definitions FSR0H_SHAD_FSR0H_SHAD_POSN equ 0000h FSR0H_SHAD_FSR0H_SHAD_POSITION equ 0000h FSR0H_SHAD_FSR0H_SHAD_SIZE equ 0008h FSR0H_SHAD_FSR0H_SHAD_LENGTH equ 0008h FSR0H_SHAD_FSR0H_SHAD_MASK equ 00FFh // Register: FSR1L_SHAD FSR1L_SHAD equ 0FEAh // bitfield definitions FSR1L_SHAD_FSR1L_SHAD_POSN equ 0000h FSR1L_SHAD_FSR1L_SHAD_POSITION equ 0000h FSR1L_SHAD_FSR1L_SHAD_SIZE equ 0008h FSR1L_SHAD_FSR1L_SHAD_LENGTH equ 0008h FSR1L_SHAD_FSR1L_SHAD_MASK equ 00FFh // Register: FSR1H_SHAD FSR1H_SHAD equ 0FEBh // bitfield definitions FSR1H_SHAD_FSR1H_SHAD_POSN equ 0000h FSR1H_SHAD_FSR1H_SHAD_POSITION equ 0000h FSR1H_SHAD_FSR1H_SHAD_SIZE equ 0008h FSR1H_SHAD_FSR1H_SHAD_LENGTH equ 0008h FSR1H_SHAD_FSR1H_SHAD_MASK equ 00FFh // Register: STKPTR STKPTR equ 0FEDh // bitfield definitions STKPTR_STKPTR_POSN equ 0000h STKPTR_STKPTR_POSITION equ 0000h STKPTR_STKPTR_SIZE equ 0005h STKPTR_STKPTR_LENGTH equ 0005h STKPTR_STKPTR_MASK equ 001Fh // Register: TOSL TOSL equ 0FEEh // bitfield definitions TOSL_TOSL_POSN equ 0000h TOSL_TOSL_POSITION equ 0000h TOSL_TOSL_SIZE equ 0008h TOSL_TOSL_LENGTH equ 0008h TOSL_TOSL_MASK equ 00FFh // Register: TOSH TOSH equ 0FEFh // bitfield definitions TOSH_TOSH_POSN equ 0000h TOSH_TOSH_POSITION equ 0000h TOSH_TOSH_SIZE equ 0007h TOSH_TOSH_LENGTH equ 0007h TOSH_TOSH_MASK equ 007Fh /* * Bit Access Macros */ #ifndef BANKMASK #define BANKMASK(addr) ((addr)&07Fh) #endif #define ABDEN BANKMASK(BAUDCON), 0 #define ABDOVF BANKMASK(BAUDCON), 7 #define ACKDT BANKMASK(SSP1CON2), 5 #define ACKEN BANKMASK(SSP1CON2), 4 #define ACKSTAT BANKMASK(SSP1CON2), 6 #define ACKTIM BANKMASK(SSP1CON3), 7 #define ACTEN BANKMASK(ACTCON), 7 #define ACTIE BANKMASK(PIE2), 1 #define ACTIF BANKMASK(PIR2), 1 #define ACTLOCK BANKMASK(ACTCON), 3 #define ACTORS BANKMASK(ACTCON), 1 #define ACTSRC BANKMASK(ACTCON), 4 #define ACTUD BANKMASK(ACTCON), 6 #define ACTVIE BANKMASK(UIE), 2 #define ACTVIF BANKMASK(UIR), 2 #define ADCS0 BANKMASK(ADCON1), 4 #define ADCS1 BANKMASK(ADCON1), 5 #define ADCS2 BANKMASK(ADCON1), 6 #define ADDEN BANKMASK(RCSTA), 3 #define ADDR0 BANKMASK(UADDR), 0 #define ADDR1 BANKMASK(UADDR), 1 #define ADDR2 BANKMASK(UADDR), 2 #define ADDR3 BANKMASK(UADDR), 3 #define ADDR4 BANKMASK(UADDR), 4 #define ADDR5 BANKMASK(UADDR), 5 #define ADDR6 BANKMASK(UADDR), 6 #define ADFM BANKMASK(ADCON1), 7 #define ADFVR0 BANKMASK(FVRCON), 0 #define ADFVR1 BANKMASK(FVRCON), 1 #define ADGO BANKMASK(ADCON0), 1 #define ADIE BANKMASK(PIE1), 6 #define ADIF BANKMASK(PIR1), 6 #define ADON BANKMASK(ADCON0), 0 #define ADPREF0 BANKMASK(ADCON1), 0 #define ADPREF1 BANKMASK(ADCON1), 1 #define AHEN BANKMASK(SSP1CON3), 1 #define ANSA4 BANKMASK(ANSELA), 4 #define ANSC0 BANKMASK(ANSELC), 0 #define ANSC1 BANKMASK(ANSELC), 1 #define ANSC2 BANKMASK(ANSELC), 2 #define ANSC3 BANKMASK(ANSELC), 3 #define BCL1IE BANKMASK(PIE2), 3 #define BCL1IF BANKMASK(PIR2), 3 #define BF BANKMASK(SSP1STAT), 0 #define BOEN BANKMASK(SSP1CON3), 4 #define BORFS BANKMASK(BORCON), 6 #define BORRDY BANKMASK(BORCON), 0 #define BRG16 BANKMASK(BAUDCON), 3 #define BRGH BANKMASK(TXSTA), 2 #define BSR0 BANKMASK(BSR), 0 #define BSR1 BANKMASK(BSR), 1 #define BSR2 BANKMASK(BSR), 2 #define BSR3 BANKMASK(BSR), 3 #define BSR4 BANKMASK(BSR), 4 #define BTOEE BANKMASK(UEIE), 4 #define BTOEF BANKMASK(UEIR), 4 #define BTSEE BANKMASK(UEIE), 7 #define BTSEF BANKMASK(UEIR), 7 #define C1HYS BANKMASK(CM1CON0), 1 #define C1IE BANKMASK(PIE2), 5 #define C1IF BANKMASK(PIR2), 5 #define C1INTN BANKMASK(CM1CON1), 6 #define C1INTP BANKMASK(CM1CON1), 7 #define C1NCH0 BANKMASK(CM1CON1), 0 #define C1NCH1 BANKMASK(CM1CON1), 1 #define C1NCH2 BANKMASK(CM1CON1), 2 #define C1OE BANKMASK(CM1CON0), 5 #define C1ON BANKMASK(CM1CON0), 7 #define C1OUT BANKMASK(CM1CON0), 6 #define C1PCH0 BANKMASK(CM1CON1), 4 #define C1PCH1 BANKMASK(CM1CON1), 5 #define C1POL BANKMASK(CM1CON0), 4 #define C1SP BANKMASK(CM1CON0), 2 #define C1SYNC BANKMASK(CM1CON0), 0 #define C2HYS BANKMASK(CM2CON0), 1 #define C2IE BANKMASK(PIE2), 6 #define C2IF BANKMASK(PIR2), 6 #define C2INTN BANKMASK(CM2CON1), 6 #define C2INTP BANKMASK(CM2CON1), 7 #define C2NCH0 BANKMASK(CM2CON1), 0 #define C2NCH1 BANKMASK(CM2CON1), 1 #define C2NCH2 BANKMASK(CM2CON1), 2 #define C2OE BANKMASK(CM2CON0), 5 #define C2ON BANKMASK(CM2CON0), 7 #define C2OUT BANKMASK(CM2CON0), 6 #define C2PCH0 BANKMASK(CM2CON1), 4 #define C2PCH1 BANKMASK(CM2CON1), 5 #define C2POL BANKMASK(CM2CON0), 4 #define C2SP BANKMASK(CM2CON0), 2 #define C2SYNC BANKMASK(CM2CON0), 0 #define CARRY BANKMASK(STATUS), 0 #define CDAFVR0 BANKMASK(FVRCON), 2 #define CDAFVR1 BANKMASK(FVRCON), 3 #define CFGS BANKMASK(PMCON1), 6 #define CHS0 BANKMASK(ADCON0), 2 #define CHS1 BANKMASK(ADCON0), 3 #define CHS2 BANKMASK(ADCON0), 4 #define CHS3 BANKMASK(ADCON0), 5 #define CHS4 BANKMASK(ADCON0), 6 #define CKE BANKMASK(SSP1STAT), 6 #define CKP BANKMASK(SSP1CON1), 4 #define CLKRCD0 BANKMASK(CLKRCON), 3 #define CLKRCD1 BANKMASK(CLKRCON), 4 #define CLKRDIV0 BANKMASK(CLKRCON), 0 #define CLKRDIV1 BANKMASK(CLKRCON), 1 #define CLKRDIV2 BANKMASK(CLKRCON), 2 #define CLKREN BANKMASK(CLKRCON), 7 #define CLKROE BANKMASK(CLKRCON), 6 #define CLKRSEL BANKMASK(APFCON), 7 #define CLKRSLR BANKMASK(CLKRCON), 5 #define CRC16EE BANKMASK(UEIE), 2 #define CRC16EF BANKMASK(UEIR), 2 #define CRC5EE BANKMASK(UEIE), 1 #define CRC5EF BANKMASK(UEIR), 1 #define CREN BANKMASK(RCSTA), 4 #define CSRC BANKMASK(TXSTA), 7 #define CWG1DBF0 BANKMASK(CWG1DBF), 0 #define CWG1DBF1 BANKMASK(CWG1DBF), 1 #define CWG1DBF2 BANKMASK(CWG1DBF), 2 #define CWG1DBF3 BANKMASK(CWG1DBF), 3 #define CWG1DBF4 BANKMASK(CWG1DBF), 4 #define CWG1DBF5 BANKMASK(CWG1DBF), 5 #define CWG1DBR0 BANKMASK(CWG1DBR), 0 #define CWG1DBR1 BANKMASK(CWG1DBR), 1 #define CWG1DBR2 BANKMASK(CWG1DBR), 2 #define CWG1DBR3 BANKMASK(CWG1DBR), 3 #define CWG1DBR4 BANKMASK(CWG1DBR), 4 #define CWG1DBR5 BANKMASK(CWG1DBR), 5 #define D1PSS0 BANKMASK(DACCON0), 2 #define D1PSS1 BANKMASK(DACCON0), 3 #define DACEN BANKMASK(DACCON0), 7 #define DACOE1 BANKMASK(DACCON0), 5 #define DACOE2 BANKMASK(DACCON0), 4 #define DACR0 BANKMASK(DACCON1), 0 #define DACR1 BANKMASK(DACCON1), 1 #define DACR2 BANKMASK(DACCON1), 2 #define DACR3 BANKMASK(DACCON1), 3 #define DACR4 BANKMASK(DACCON1), 4 #define DFN8EE BANKMASK(UEIE), 3 #define DFN8EF BANKMASK(UEIR), 3 #define DHEN BANKMASK(SSP1CON3), 0 #define DIR BANKMASK(USTAT), 2 #define D_nA BANKMASK(SSP1STAT), 5 #define ENDP0 BANKMASK(USTAT), 3 #define ENDP1 BANKMASK(USTAT), 4 #define ENDP2 BANKMASK(USTAT), 5 #define ENDP3 BANKMASK(USTAT), 6 #define FERR BANKMASK(RCSTA), 2 #define FREE BANKMASK(PMCON1), 4 #define FRM0 BANKMASK(UFRML), 0 #define FRM1 BANKMASK(UFRML), 1 #define FRM10 BANKMASK(UFRMH), 2 #define FRM2 BANKMASK(UFRML), 2 #define FRM3 BANKMASK(UFRML), 3 #define FRM4 BANKMASK(UFRML), 4 #define FRM5 BANKMASK(UFRML), 5 #define FRM6 BANKMASK(UFRML), 6 #define FRM7 BANKMASK(UFRML), 7 #define FRM8 BANKMASK(UFRMH), 0 #define FRM9 BANKMASK(UFRMH), 1 #define FSEN BANKMASK(UCFG), 2 #define FVREN BANKMASK(FVRCON), 7 #define FVRRDY BANKMASK(FVRCON), 6 #define G1ARSEN BANKMASK(CWG1CON2), 6 #define G1ASDLA0 BANKMASK(CWG1CON1), 4 #define G1ASDLA1 BANKMASK(CWG1CON1), 5 #define G1ASDLB0 BANKMASK(CWG1CON1), 6 #define G1ASDLB1 BANKMASK(CWG1CON1), 7 #define G1ASDSC1 BANKMASK(CWG1CON2), 2 #define G1ASDSC2 BANKMASK(CWG1CON2), 3 #define G1ASDSFLT BANKMASK(CWG1CON2), 1 #define G1ASE BANKMASK(CWG1CON2), 7 #define G1CS0 BANKMASK(CWG1CON0), 0 #define G1EN BANKMASK(CWG1CON0), 7 #define G1IS0 BANKMASK(CWG1CON1), 0 #define G1IS1 BANKMASK(CWG1CON1), 1 #define G1OEA BANKMASK(CWG1CON0), 5 #define G1OEB BANKMASK(CWG1CON0), 6 #define G1POLA BANKMASK(CWG1CON0), 3 #define G1POLB BANKMASK(CWG1CON0), 4 #define GCEN BANKMASK(SSP1CON2), 7 #define GIE BANKMASK(INTCON), 7 #define GO BANKMASK(ADCON0), 1 #define GO_nDONE BANKMASK(ADCON0), 1 #define HFIOFR BANKMASK(OSCSTAT), 4 #define HFIOFS BANKMASK(OSCSTAT), 0 #define IDLEIE BANKMASK(UIE), 4 #define IDLEIF BANKMASK(UIR), 4 #define INTE BANKMASK(INTCON), 4 #define INTEDG BANKMASK(OPTION_REG), 6 #define INTF BANKMASK(INTCON), 1 #define IOCAF0 BANKMASK(IOCAF), 0 #define IOCAF1 BANKMASK(IOCAF), 1 #define IOCAF3 BANKMASK(IOCAF), 3 #define IOCAF4 BANKMASK(IOCAF), 4 #define IOCAF5 BANKMASK(IOCAF), 5 #define IOCAN0 BANKMASK(IOCAN), 0 #define IOCAN1 BANKMASK(IOCAN), 1 #define IOCAN3 BANKMASK(IOCAN), 3 #define IOCAN4 BANKMASK(IOCAN), 4 #define IOCAN5 BANKMASK(IOCAN), 5 #define IOCAP0 BANKMASK(IOCAP), 0 #define IOCAP1 BANKMASK(IOCAP), 1 #define IOCAP3 BANKMASK(IOCAP), 3 #define IOCAP4 BANKMASK(IOCAP), 4 #define IOCAP5 BANKMASK(IOCAP), 5 #define IOCIE BANKMASK(INTCON), 3 #define IOCIF BANKMASK(INTCON), 0 #define IRCF0 BANKMASK(OSCCON), 2 #define IRCF1 BANKMASK(OSCCON), 3 #define IRCF2 BANKMASK(OSCCON), 4 #define IRCF3 BANKMASK(OSCCON), 5 #define LATA4 BANKMASK(LATA), 4 #define LATA5 BANKMASK(LATA), 5 #define LATC0 BANKMASK(LATC), 0 #define LATC1 BANKMASK(LATC), 1 #define LATC2 BANKMASK(LATC), 2 #define LATC3 BANKMASK(LATC), 3 #define LATC4 BANKMASK(LATC), 4 #define LATC5 BANKMASK(LATC), 5 #define LFIOFR BANKMASK(OSCSTAT), 1 #define LWLO BANKMASK(PMCON1), 5 #define MC1OUT BANKMASK(CMOUT), 0 #define MC2OUT BANKMASK(CMOUT), 1 #define OERR BANKMASK(RCSTA), 1 #define OSFIE BANKMASK(PIE2), 7 #define OSFIF BANKMASK(PIR2), 7 #define OSTS BANKMASK(OSCSTAT), 5 #define P2SEL BANKMASK(APFCON), 2 #define PCIE BANKMASK(SSP1CON3), 6 #define PEIE BANKMASK(INTCON), 6 #define PEN BANKMASK(SSP1CON2), 2 #define PIDEE BANKMASK(UEIE), 0 #define PIDEF BANKMASK(UEIR), 0 #define PKTDIS BANKMASK(UCON), 4 #define PLLRDY BANKMASK(OSCSTAT), 6 #define PPB0 BANKMASK(UCFG), 0 #define PPB1 BANKMASK(UCFG), 1 #define PPBI BANKMASK(USTAT), 1 #define PPBRST BANKMASK(UCON), 6 #define PS0 BANKMASK(OPTION_REG), 0 #define PS1 BANKMASK(OPTION_REG), 1 #define PS2 BANKMASK(OPTION_REG), 2 #define PSA BANKMASK(OPTION_REG), 3 #define PWM1DCH0 BANKMASK(PWM1DCH), 0 #define PWM1DCH1 BANKMASK(PWM1DCH), 1 #define PWM1DCH2 BANKMASK(PWM1DCH), 2 #define PWM1DCH3 BANKMASK(PWM1DCH), 3 #define PWM1DCH4 BANKMASK(PWM1DCH), 4 #define PWM1DCH5 BANKMASK(PWM1DCH), 5 #define PWM1DCH6 BANKMASK(PWM1DCH), 6 #define PWM1DCH7 BANKMASK(PWM1DCH), 7 #define PWM1DCL0 BANKMASK(PWM1DCL), 6 #define PWM1DCL1 BANKMASK(PWM1DCL), 7 #define PWM1EN BANKMASK(PWM1CON), 7 #define PWM1OE BANKMASK(PWM1CON), 6 #define PWM1OUT BANKMASK(PWM1CON), 5 #define PWM1POL BANKMASK(PWM1CON), 4 #define PWM2DCH0 BANKMASK(PWM2DCH), 0 #define PWM2DCH1 BANKMASK(PWM2DCH), 1 #define PWM2DCH2 BANKMASK(PWM2DCH), 2 #define PWM2DCH3 BANKMASK(PWM2DCH), 3 #define PWM2DCH4 BANKMASK(PWM2DCH), 4 #define PWM2DCH5 BANKMASK(PWM2DCH), 5 #define PWM2DCH6 BANKMASK(PWM2DCH), 6 #define PWM2DCH7 BANKMASK(PWM2DCH), 7 #define PWM2DCL0 BANKMASK(PWM2DCL), 6 #define PWM2DCL1 BANKMASK(PWM2DCL), 7 #define PWM2EN BANKMASK(PWM2CON), 7 #define PWM2OE BANKMASK(PWM2CON), 6 #define PWM2OUT BANKMASK(PWM2CON), 5 #define PWM2POL BANKMASK(PWM2CON), 4 #define RA0 BANKMASK(PORTA), 0 #define RA1 BANKMASK(PORTA), 1 #define RA3 BANKMASK(PORTA), 3 #define RA4 BANKMASK(PORTA), 4 #define RA5 BANKMASK(PORTA), 5 #define RC0 BANKMASK(PORTC), 0 #define RC1 BANKMASK(PORTC), 1 #define RC2 BANKMASK(PORTC), 2 #define RC3 BANKMASK(PORTC), 3 #define RC4 BANKMASK(PORTC), 4 #define RC5 BANKMASK(PORTC), 5 #define RCEN BANKMASK(SSP1CON2), 3 #define RCIDL BANKMASK(BAUDCON), 6 #define RCIE BANKMASK(PIE1), 5 #define RCIF BANKMASK(PIR1), 5 #define RD BANKMASK(PMCON1), 0 #define RESUME BANKMASK(UCON), 2 #define RSEN BANKMASK(SSP1CON2), 1 #define RX9 BANKMASK(RCSTA), 6 #define RX9D BANKMASK(RCSTA), 0 #define R_nW BANKMASK(SSP1STAT), 2 #define SBCDE BANKMASK(SSP1CON3), 2 #define SBOREN BANKMASK(BORCON), 7 #define SCIE BANKMASK(SSP1CON3), 5 #define SCKP BANKMASK(BAUDCON), 4 #define SCS0 BANKMASK(OSCCON), 0 #define SCS1 BANKMASK(OSCCON), 1 #define SDAHT BANKMASK(SSP1CON3), 3 #define SDOSEL BANKMASK(APFCON), 6 #define SE0 BANKMASK(UCON), 5 #define SEN BANKMASK(SSP1CON2), 0 #define SENDB BANKMASK(TXSTA), 3 #define SMP BANKMASK(SSP1STAT), 7 #define SOFIE BANKMASK(UIE), 6 #define SOFIF BANKMASK(UIR), 6 #define SOSCR BANKMASK(OSCSTAT), 7 #define SPEN BANKMASK(RCSTA), 7 #define SPLLEN BANKMASK(OSCCON), 7 #define SPLLMULT BANKMASK(OSCCON), 6 #define SREN BANKMASK(RCSTA), 5 #define SSP1EN BANKMASK(SSP1CON1), 5 #define SSP1IE BANKMASK(PIE1), 3 #define SSP1IF BANKMASK(PIR1), 3 #define SSP1M0 BANKMASK(SSP1CON1), 0 #define SSP1M1 BANKMASK(SSP1CON1), 1 #define SSP1M2 BANKMASK(SSP1CON1), 2 #define SSP1M3 BANKMASK(SSP1CON1), 3 #define SSP1OV BANKMASK(SSP1CON1), 6 #define SSPEN BANKMASK(SSP1CON1), 5 #define SSPOV BANKMASK(SSP1CON1), 6 #define SSSEL BANKMASK(APFCON), 5 #define STALLIE BANKMASK(UIE), 5 #define STALLIF BANKMASK(UIR), 5 #define STKOVF BANKMASK(PCON), 7 #define STKUNF BANKMASK(PCON), 6 #define SUSPND BANKMASK(UCON), 1 #define SWDTEN BANKMASK(WDTCON), 0 #define SYNC BANKMASK(TXSTA), 4 #define T0CS BANKMASK(OPTION_REG), 5 #define T0IE BANKMASK(INTCON), 5 #define T0IF BANKMASK(INTCON), 2 #define T0SE BANKMASK(OPTION_REG), 4 #define T1CKPS0 BANKMASK(T1CON), 4 #define T1CKPS1 BANKMASK(T1CON), 5 #define T1GGO_nDONE BANKMASK(T1GCON), 3 #define T1GPOL BANKMASK(T1GCON), 6 #define T1GSEL BANKMASK(APFCON), 3 #define T1GSPM BANKMASK(T1GCON), 4 #define T1GSS0 BANKMASK(T1GCON), 0 #define T1GSS1 BANKMASK(T1GCON), 1 #define T1GTM BANKMASK(T1GCON), 5 #define T1GVAL BANKMASK(T1GCON), 2 #define T1OSCEN BANKMASK(T1CON), 3 #define T2CKPS0 BANKMASK(T2CON), 0 #define T2CKPS1 BANKMASK(T2CON), 1 #define T2OUTPS0 BANKMASK(T2CON), 3 #define T2OUTPS1 BANKMASK(T2CON), 4 #define T2OUTPS2 BANKMASK(T2CON), 5 #define T2OUTPS3 BANKMASK(T2CON), 6 #define TMR0CS BANKMASK(OPTION_REG), 5 #define TMR0IE BANKMASK(INTCON), 5 #define TMR0IF BANKMASK(INTCON), 2 #define TMR0SE BANKMASK(OPTION_REG), 4 #define TMR1CS0 BANKMASK(T1CON), 6 #define TMR1CS1 BANKMASK(T1CON), 7 #define TMR1GE BANKMASK(T1GCON), 7 #define TMR1GIE BANKMASK(PIE1), 7 #define TMR1GIF BANKMASK(PIR1), 7 #define TMR1IE BANKMASK(PIE1), 0 #define TMR1IF BANKMASK(PIR1), 0 #define TMR1ON BANKMASK(T1CON), 0 #define TMR2IE BANKMASK(PIE1), 1 #define TMR2IF BANKMASK(PIR1), 1 #define TMR2ON BANKMASK(T2CON), 2 #define TRIGSEL0 BANKMASK(ADCON2), 4 #define TRIGSEL1 BANKMASK(ADCON2), 5 #define TRIGSEL2 BANKMASK(ADCON2), 6 #define TRISA4 BANKMASK(TRISA), 4 #define TRISA5 BANKMASK(TRISA), 5 #define TRISC0 BANKMASK(TRISC), 0 #define TRISC1 BANKMASK(TRISC), 1 #define TRISC2 BANKMASK(TRISC), 2 #define TRISC3 BANKMASK(TRISC), 3 #define TRISC4 BANKMASK(TRISC), 4 #define TRISC5 BANKMASK(TRISC), 5 #define TRMT BANKMASK(TXSTA), 1 #define TRNIE BANKMASK(UIE), 3 #define TRNIF BANKMASK(UIR), 3 #define TUN0 BANKMASK(OSCTUNE), 0 #define TUN1 BANKMASK(OSCTUNE), 1 #define TUN2 BANKMASK(OSCTUNE), 2 #define TUN3 BANKMASK(OSCTUNE), 3 #define TUN4 BANKMASK(OSCTUNE), 4 #define TUN5 BANKMASK(OSCTUNE), 5 #define TUN6 BANKMASK(OSCTUNE), 6 #define TX9 BANKMASK(TXSTA), 6 #define TX9D BANKMASK(TXSTA), 0 #define TXEN BANKMASK(TXSTA), 5 #define TXIE BANKMASK(PIE1), 4 #define TXIF BANKMASK(PIR1), 4 #define UA BANKMASK(SSP1STAT), 1 #define UERRIE BANKMASK(UIE), 1 #define UERRIF BANKMASK(UIR), 1 #define UPUEN BANKMASK(UCFG), 4 #define URSTIE BANKMASK(UIE), 0 #define URSTIF BANKMASK(UIR), 0 #define USBEN BANKMASK(UCON), 3 #define USBIE BANKMASK(PIE2), 2 #define USBIF BANKMASK(PIR2), 2 #define UTEYE BANKMASK(UCFG), 7 #define VREGPM0 BANKMASK(VREGCON), 0 #define VREGPM1 BANKMASK(VREGCON), 1 #define WCOL BANKMASK(SSP1CON1), 7 #define WDTPS0 BANKMASK(WDTCON), 1 #define WDTPS1 BANKMASK(WDTCON), 2 #define WDTPS2 BANKMASK(WDTCON), 3 #define WDTPS3 BANKMASK(WDTCON), 4 #define WDTPS4 BANKMASK(WDTCON), 5 #define WPUA3 BANKMASK(WPUA), 3 #define WPUA4 BANKMASK(WPUA), 4 #define WPUA5 BANKMASK(WPUA), 5 #define WR BANKMASK(PMCON1), 1 #define WREN BANKMASK(PMCON1), 2 #define WRERR BANKMASK(PMCON1), 3 #define WUE BANKMASK(BAUDCON), 1 #define ZERO BANKMASK(STATUS), 2 #define nBOR BANKMASK(PCON), 0 #define nPD BANKMASK(STATUS), 3 #define nPOR BANKMASK(PCON), 1 #define nRI BANKMASK(PCON), 2 #define nRMCLR BANKMASK(PCON), 3 #define nRWDT BANKMASK(PCON), 4 #define nT1SYNC BANKMASK(T1CON), 2 #define nTO BANKMASK(STATUS), 4 #define nWPUEN BANKMASK(OPTION_REG), 7 #endif // _PIC16F1455_INC_